公开(公告)号：US11929289B2

公开(公告)日：2024-03-12

申请号：US17958805

申请日：2022-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US11062961B2

公开(公告)日：2021-07-13

申请号：US16408912

申请日：2019-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin Yoo ,  Juyoun Kim ,  Hyungjoo Na ,  Bongseok Suh ,  Jooho Jung ,  Euichul Hwang ,  Sungmoon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/118 ,  H01L21/762

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US20240282834A1

公开(公告)日：2024-08-22

申请号：US18649553

申请日：2024-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun Kim ,  Hyung Jong Lee ,  Seulgi Yun ,  Seki Hong

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

公开(公告)号：US11462442B2

公开(公告)日：2022-10-04

申请号：US17335174

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US11380686B2

公开(公告)日：2022-07-05

申请号：US17101472

申请日：2020-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Seulgi Yun ,  Seki Hong

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes first and second transistors on a substrate. The first transistor includes a first N-type active region, a first gate electrode having a first work function layer, and a first gate dielectric layer having high-k dielectrics containing La. The first work function layer includes a first layer having TiON, a second layer having TiN or TiON, a third layer having TiON, a fourth layer having TiN, and a fifth layer having TiAlC. The second transistor includes a first P-type active region, a second gate electrode having a second work function layer, and a second gate dielectric layer having high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer.

公开(公告)号：US11164869B2

公开(公告)日：2021-11-02

申请号：US16848902

申请日：2020-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewon Ha ,  Juyoun Kim ,  Sang Min Lee ,  Moon-Sun Hong ,  Seki Hong

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having an active region, and first to third transistors on the active region of the substrate, each of the first to third transistors including a dielectric layer on the substrate, a metal layer on the dielectric layer, a barrier layer between the dielectric layer and the metal layer, and a work function layer between the dielectric layer and the barrier layer, wherein the barrier layer of the third transistor is in contact with the dielectric layer of the third transistor, and wherein a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor and less than a threshold voltage of the third transistor.

公开(公告)号：US20210328035A1

公开(公告)日：2021-10-21

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US10388574B2

公开(公告)日：2019-08-20

申请号：US15468631

申请日：2017-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US20240339514A1

公开(公告)日：2024-10-10

申请号：US18743588

申请日：2024-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US11901358B2

公开(公告)日：2024-02-13

申请号：US17497449

申请日：2021-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsoo Seo ,  Sangjung Kang ,  Juyoun Kim ,  Seulgi Yun ,  Seki Hong

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure on a substrate, partially removing the dummy gate structure to form a first opening that divides the dummy gate structure, forming a first division pattern structure in the first opening, replacing the dummy gate structure with a gate structure, removing the first division pattern structure to form a second opening, removing a portion of the gate structure from a sidewall of the second opening to enlarge the second opening, and forming a second division pattern in the enlarged second opening.