公开(公告)号：US20250125253A1

公开(公告)日：2025-04-17

申请号：US18618469

申请日：2024-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongsuk OH ,  Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Provided is a semiconductor device which includes: a transistor structure; a plurality of 1st metal lines above the transistor structure; and a plurality of 1st vias formed on selected 1st metal lines, respectively, among the plurality of 1st metal lines; a 2nd via formed on a 1st via among the plurality of 1st vias; and a 2nd metal line on the 2nd via, wherein the 1st metal lines are arranged in a 1st direction and extended in a 2nd direction which intersects the 1st direction, and the 2nd metal line is extended in the 1st direction, and wherein the plurality of 1st vias comprise at least one dummy via which is not connected to any metal line thereabove other than an underlying 1st metal line among the selected 1st metal lines.

公开(公告)号：US20240290853A1

公开(公告)日：2024-08-29

申请号：US18373058

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41766 ,  H01L29/401

Abstract: Provided is a semiconductor device which includes: a backside contact plug, formed at a back side of the semiconductor device, below a source/drain region connected to the backside contact plug, wherein the backside contact plug includes a 1st portion which is not vertically overlapped by the circuit element.

公开(公告)号：US20230343698A1

公开(公告)日：2023-10-26

申请号：US17883073

申请日：2022-08-08

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jaemyung CHOI ,  Tae Sun KIM ,  Janggeun LEE ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76832 ,  H01L21/76807 ,  H01L23/53295

Abstract: Provided is a semiconductor device including at least one front-end-of-line (FEOL) element connected to an interconnect structure, the interconnect structure including: a 1st metal pattern or via structure with a spacer structure on a sidewall thereof; and a 1st interlayer dielectric (ILD) layer formed at sides of the 1st metal pattern or via structure with the spacer structure on the sidewall thereof, wherein the spacer structure includes a dielectric material different from a material included in the 1st ILD layer.

公开(公告)号：US20240395900A1

公开(公告)日：2024-11-28

申请号：US18380951

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Jason MARTINEAU ,  Kang-ill SEO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure configured to control the channel structure; a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region; a backside isolation structure at a lower portion of the semiconductor device; and a 1st contact spacer on the backside source/drain contact structure, wherein the 1st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure.

公开(公告)号：US20240379780A1

公开(公告)日：2024-11-14

申请号：US18239552

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keumseok PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device whch includes: a 1st source/drain region connected to a 1st channel structure; a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure; a channel isolation layer between the 1st channel structure and the 2nd channel structure; a source/drain isolation layer between the 1st source/drain region and the 2nd source/drain region; and a blocking structure between the channel isolation layer and the source/drain isolation layer, wherein an entire width of the blocking structure in a channel-length direction is verically below a lateral edge portion of the 2nd source/drain region.

公开(公告)号：US20240290866A1

公开(公告)日：2024-08-29

申请号：US18540280

申请日：2023-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Taesun KIM ,  Myunghoon JUNG ,  Kang-ill SEO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A system and a method are disclosed for forming a bottle-neck shaped backside contact structure in a semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side partially within the first source/drain structure, a second side contacting a backside power rail, and a liner extending from the first side to the backside power rail. The liner includes a first region comprised of either a Ta silicide liner or a Ti silicide liner, a second region comprised of a Ti/TiN liner and a third region comprised of either a Ta silicide liner or a Ti silicide liner. The backside contact structure includes a first portion having a positive slope and a second portion, adjacent to the first portion, having no slope.

公开(公告)号：US20240290690A1

公开(公告)日：2024-08-29

申请号：US18220432

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae PARK ,  Kang-ill SEO

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device in which a large-CPP area includes a 1st source/drain structure; a 1st frontside contact structure, at a front side of the semiconductor device, connected to the 1st source/drain structure; a 1st via structure, at a lateral side of the 1st source/drain structure, connected to the 1st frontside contact structure; a 2nd via structure on the 1st frontside via structure; a 1st frontside metal line, at the front side of the semiconductor device, connected to the 2nd via structure; and a 1st backside metal line, at a back side of the semiconductor device, connected to the 1st via structure.

公开(公告)号：US20240203882A1

公开(公告)日：2024-06-20

申请号：US18197381

申请日：2023-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongjin LEE ,  Jaejik BAEK ,  Myunghoon JUNG ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is a method of manufacturing an integrated circuit device. The method includes forming a semiconductor device, wherein the semiconductor device has one or more source/drain structures, one or more channel structures and wherein the substrate is on a first side of the semiconductor device. The method also includes forming a back-end-of-line (BEOL) region and forming a bottle-neck shaped backside contact structure in the substrate and in contact with a first source/drain structure of the semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side contacting the first source/drain structure, a second side contacting a backside power rail, and sidewalls extending from the first source/drain structure to the backside power rail; and wherein the backside contact structure has a first region having a positive slope and a second region, adjacent to the first region, having no slope.

公开(公告)号：US20230352528A1

公开(公告)日：2023-11-02

申请号：US17945695

申请日：2022-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keumseok PARK ,  Sooyoung PARK ,  Kang-ill SEO ,  Jaehong LEE

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/0847 ,  H01L27/0924

Abstract: Provided is a multi-stack semiconductor device including: a substrate; a lower-stack nanosheet transistor including two or more lower channel layers surrounded by a lower gate structure, the lower channel layers connecting lower source/drain regions; and an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and including two or more upper channel layers surrounded by an upper gate structure, the upper channel layers connecting upper source/drain regions, wherein the lower-stack nanosheet transistor and the upper-stack nanosheet transistor have at least one of: a difference between a thickness of one of the lower channel layers and a thickness of one of the upper channel layers; and a difference between a thickness of the lower gate structure between two adjacent lower channel layers and a thickness of the upper gate structure between two adjacent upper channel layers.

公开(公告)号：US20250167106A1

公开(公告)日：2025-05-22

申请号：US18738802

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Provided is a semiconductor device which includes: a base layer including at least one transistor structure; and an interconnect structure above the base layer in a 3rd direction, wherein the interconnect structure includes a 1st metal line, a 2nd metal line, and at least one another metal line extended in a 1st direction and arranged at a 2nd direction, wherein at least a 1st portion of the 1st metal line having a 1st metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction has a greater height than at least a 1st portion of the 2nd metal line having a 2nd metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction, wherein the 1st metal-to-metal distance is greater than the 2nd metal-to-metal distance, and wherein the 1st direction and the 2nd direction horizontally intersect each other, and vertically intersect the 3rd direction.