公开(公告)号：US20160055905A1

公开(公告)日：2016-02-25

申请号：US14832229

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun Lee ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C7/20 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Abstract translation: 提供了非易失性存储器件和非易失性存储器件的驱动方法。 非易失性存储器件可以包括多个存储器组，由多个存储器组共享的读取全局位线，由多个存储器组共享的写入全局位线，与读取的全局位线连接的读取电路，并执行 读取操作和与写入全局位线连接的放电控制电路，并且在上电操作之后的初始化间隔期间主要对写入全局位线进行放电。

公开(公告)号：US20250103233A1

公开(公告)日：2025-03-27

申请号：US18741452

申请日：2024-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Jin Lee ,  Kirock Kwon ,  Chanho Jung

IPC: G06F3/06

Abstract: A storage device includes a non-volatile memory and a storage controller. The non-volatile memory includes a plurality of storage regions, and the plurality of storage regions include a first storage region and a second storage region which have different types. The storage controller programs data from a host device in the first storage region, based on safety level information of the host device and remaining storage region information of the non-volatile memory. Based on the safety level information and the remaining storage region information, the storage controller migrates the data programmed in the first storage region to the second storage region or returns the data migrated to the second storage region to the first storage region.

公开(公告)号：US09952789B2

公开(公告)日：2018-04-24

申请号：US15393844

申请日：2016-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Jin Lee

IPC: H03M13/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/35

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/29 ,  H03M13/356

Abstract: A memory system includes a nonvolatile memory module and a memory controller. The nonvolatile memory module includes a plurality of memory chips and a module controller disposed on a printed circuit board. The module controller controls operations of the plurality of memory chips. Each of the plurality of memory chips includes a plurality of nonvolatile memory cells and operates in an operation mode. The operation mode is either a memory mode or a storage mode. The memory controller performs a write operation and a read operation on the nonvolatile memory module, and performs a first error check and correction (ECC) operation on data communicated with the nonvolatile memory module. One of the module controller or the plurality of memory chips performs a second ECC operation on data stored in the plurality of memory chips based on the operation mode of the plurality of memory chips.

公开(公告)号：US09659644B2

公开(公告)日：2017-05-23

申请号：US14612640

申请日：2015-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon Jeong ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Jae-Yun Lee

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.