公开(公告)号：US10897687B2

公开(公告)日：2021-01-19

申请号：US16566058

申请日：2019-09-10

Applicant: Samsung Electronics Co., Ltd. ,  INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

Inventor： Taejun Kwon ,  Seongil Hahm ,  Jonghoon Shin ,  Kyoungwoo Lee ,  Hyunchoong Kim

IPC: H04W4/02 ,  H04W4/029 ,  H04W4/021 ,  H04W4/33 ,  G01S5/14 ,  G01S5/02 ,  G01S19/03 ,  G01S19/48

Abstract: An electronic device and a method for identifying a location by the electronic device are provided. The electronic device includes a display, a processor electrically connected with the display and a memory, and the memory storing instructions executed by the processor. The processor is configured to obtain a plurality of locations in a space-of-interest, detect a wireless signal from at least one external electronic device located in the space-of-interest or an adjacent area, obtain detection frequency data according to a frequency of detection of the wireless signal, and identify a current location of the electronic device based on at least part of the obtained detection frequency data.

公开(公告)号：US20240203872A1

公开(公告)日：2024-06-20

申请号：US18590793

申请日：2024-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun Lim ,  Wookyung You ,  Kyoungwoo Lee ,  Juyoung Jung ,  Il Sup Kim ,  Chin Kim ,  Kyoungpil Park ,  Jinhyung Park

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06

CPC classification number: H01L23/5228 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L27/0688

Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer, and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

公开(公告)号：US11948883B2

公开(公告)日：2024-04-02

申请号：US17221191

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun Lim ,  Wookyung You ,  Kyoungwoo Lee ,  Juyoung Jung ,  Il Sup Kim ,  Chin Kim ,  Kyoungpil Park ,  Jinhyung Park

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L27/0688

Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

公开(公告)号：US09257389B2

公开(公告)日：2016-02-09

申请号：US14448115

申请日：2014-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WooJin Jang ,  Kyoungwoo Lee

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2224/13

Abstract: A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.

Abstract translation: 提供一种形成半导体器件的金属互连的方法。 该方法包括形成包括开口的低k电介质层; 形成保形地覆盖所述开口的底部表面和内侧壁的阻挡金属图案; 形成露出所述开口中的所述阻挡金属图案的内侧壁的一部分的金属图案; 使用选择性化学气相沉积工艺在金属图案和低k电介质层的顶表面上形成金属覆盖层，其中金属图案上的金属覆盖层的厚度大于金属覆盖层的厚度 在低k电介质层上; 以及通过将金属覆盖层平坦化到低k电介质层的顶表面来形成覆盖金属图案的顶表面的金属覆盖图案。