公开(公告)号：US20180074124A1

公开(公告)日：2018-03-15

申请号：US15365808

申请日：2016-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31718 ,  G01R31/2894 ,  G01R31/3177

Abstract: A method of circuit yield analysis for evaluating rare failure events existing in multiple disjoint failure regions defined by a multi-dimensional parametric space, the method including performing initial sampling to detect failed samples respectively located at multiple failure regions in the multi-dimensional parametric space, performing clustering to identify the failure regions, performing feature filtering to determine which parameter component is a non-principal component in affecting circuit yield, applying a dimensional reduction method on a dimension corresponding to the parameter component, optimizing an importance sampling (IS) distribution function corresponding to each of the failure regions, and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions.

公开(公告)号：US20170077311A1

公开(公告)日：2017-03-16

申请号：US15358822

申请日：2016-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing WANG ,  Woosung CHOI

IPC: H01L29/786 ,  A61B5/0482 ,  H03F3/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78624 ,  A61B5/0482 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7843 ,  H01L29/7845 ,  H03F1/0205 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2203/45116 ,  H03F2203/45118 ,  H03F2203/45288

Abstract: Neural signal amplifiers include an operational amplifier and a feedback network coupled between an output and an input thereof. The feedback network includes a tunnel field effect transistor (“TFET”) pseudo resistor that exhibits bi-directional conductivity. A drain region of the TFET may be electrically connected to the gate electrode thereof to provide a bi-directional resistor having good symmetry in terms of resistance as a function of voltage polarity.

Abstract translation: 神经信号放大器包括耦合在输出端和输入端之间的运算放大器和反馈网络。 反馈网络包括呈现双向导电性的隧道场效应晶体管（“TFET”）伪电阻器。 TFET的漏极区域可以电连接到其栅电极，以提供作为电压极性的函数的电阻方面具有良好对称性的双向电阻器。

公开(公告)号：US20160197184A1

公开(公告)日：2016-07-07

申请号：US14642918

申请日：2015-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing WANG ,  Woosung CHOI

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/28035 ,  H01L29/0688 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7843 ,  H01L29/7845

Abstract: Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region.

Abstract translation: 隧道场效应晶体管包括半导体衬底; 半导体衬底中的源极区; 半导体衬底中的漏区; 在所述源极区域和所述漏极区域之间的所述半导体衬底中的沟道区域; 以及在沟道区上方的半导体衬底上的栅电极。 源区包括具有第一导电类型的第一区域，具有不同于第一导电类型的第二导电类型的第三区域和位于第一区域和第三区域之间的具有本征导电类型的第二区域。

公开(公告)号：US10330727B2

公开(公告)日：2019-06-25

申请号：US15365808

申请日：2016-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3193 ,  G01R31/34

Abstract: A method of circuit yield analysis for evaluating rare failure events existing in multiple disjoint failure regions defined by a multi-dimensional parametric space, the method including performing initial sampling to detect failed samples respectively located at multiple failure regions in the multi-dimensional parametric space, performing clustering to identify the failure regions, performing feature filtering to determine which parameter component is a non-principal component in affecting circuit yield, applying a dimensional reduction method on a dimension corresponding to the parameter component, optimizing an importance sampling (IS) distribution function corresponding to each of the failure regions, and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions.

公开(公告)号：US20190138897A1

公开(公告)日：2019-05-09

申请号：US15951052

申请日：2018-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Zhengping Jiang ,  Weiyi Qi ,  Jing Wang ,  Woosung Choi

IPC: G06N3/08 ,  G06F17/50

Abstract: According to one embodiment of the present invention a circuit simulator configured to simulate a degraded output of a circuit including a plurality of transistors includes: a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform; a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

公开(公告)号：US10204188B2

公开(公告)日：2019-02-12

申请号：US14991124

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Nuo Xu ,  Woosung Choi

IPC: G06F17/50

Abstract: A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing a technology computer aided design data set corresponding to nominal performance of the semiconductor device, identifying a plurality of process variation sources that correspond to process variations that occur during the manufacturing of the semiconductor device, generating a nominal value look-up table of electrical parameters of the semiconductor device using nominal values of each of the plurality of process variation sources, and generating a plurality of process variation look-up tables of electrical parameters of the semiconductor device using variation values corresponding to each of the plurality of process variation sources that are identified as corresponding to the semiconductor device.

公开(公告)号：US10146896B2

公开(公告)日：2018-12-04

申请号：US15344346

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Nuo Xu ,  Woosung Choi

IPC: G06F17/00 ,  G06F17/50 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

Abstract: A method for selecting transistor design parameters. A first set of simulations is used to calculate leakage current at a plurality of sets of design parameter values, and the results are fitted with a first response surface methodology model. The first model is used to generate a function that returns a value of a selected design parameter, for which a leakage current specification is just met. A second set of simulations is used to calculate effective drive current for a plurality of sets of design parameter values, and the results are fitted with a second response surface methodology model. The second model is used, together with the first, to search for a set of design parameter values at which a worst-case effective drive current is greatest, subject to the constraint of meeting the worst-case leakage current specification.

公开(公告)号：US20160359041A9

公开(公告)日：2016-12-08

申请号：US14642918

申请日：2015-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing WANG ,  Woosung CHOI

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/28035 ,  H01L29/0688 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7843 ,  H01L29/7845

Abstract: Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region.