公开(公告)号：US10998412B2

公开(公告)日：2021-05-04

申请号：US16916643

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heon Bok Lee ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L21/285 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/10

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

公开(公告)号：US10770560B2

公开(公告)日：2020-09-08

申请号：US16214537

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk Yim ,  Kug Hwan Kim ,  Wan Don Kim ,  Jung Min Park ,  Jong Ho Park ,  Byoung Hoon Lee ,  Yong Ho Ha ,  Sang Jin Hyun ,  Hye Ri Hong

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.

公开(公告)号：US20200176575A1

公开(公告)日：2020-06-04

申请号：US16695675

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US10347763B2

公开(公告)日：2019-07-09

申请号：US15697678

申请日：2017-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo Kim ,  Dong Hyun Roh ,  Koung Min Ryu ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L27/12

Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

公开(公告)号：US20190157452A1

公开(公告)日：2019-05-23

申请号：US16028083

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin Hye Kim ,  Kyung Seok Oh ,  Gu Young Cho ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L23/532

Abstract: A semiconductor device includes a substrate and a plurality of semiconductor fins protruding from the substrate. Source/drain regions are disposed at tops of respective ones of the semiconductor fins, each having a width greater than a width of individual ones of the semiconductor fins. A gate electrode is disposed on side surfaces of the semiconductor fins below the source/drain regions. Insulating layers contact the side surfaces of the semiconductor fins and cover upper surfaces of the gate electrode.

公开(公告)号：US10269629B2

公开(公告)日：2019-04-23

申请号：US15624783

申请日：2017-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun Choi ,  Jeong Ik Kim ,  Myung Yang ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.

公开(公告)号：US20180090493A1

公开(公告)日：2018-03-29

申请号：US15643062

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Young Kwak ,  Ki Byung Park ,  Kyoung Hwan Yeo ,  Seung Jae Lee ,  Kyung Yub Jeon ,  Seung Seok Ha ,  Sang Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.

公开(公告)号：US11949012B2

公开(公告)日：2024-04-02

申请号：US17114598

申请日：2020-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Ho Park ,  Wan Don Kim ,  Weon Hong Kim ,  Hyeon Jun Baek ,  Byoung Hoon Lee ,  Jeong Hyuk Yim ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/516

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

公开(公告)号：US11282939B2

公开(公告)日：2022-03-22

申请号：US16269712

申请日：2019-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon Lee ,  Wan Don Kim ,  Jong Ho Park ,  Sang Jin Hyun

IPC: H01L29/51 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

公开(公告)号：US10714579B2

公开(公告)日：2020-07-14

申请号：US15999191

申请日：2018-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heon Bok Lee ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L21/285 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/10

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.