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公开(公告)号：US20250094127A1
公开(公告)日：2025-03-20
申请号：US18969509
申请日：2024-12-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungchul JUNG , Sang Joon KIM , Sungmeen MYUNG , Seok Ju YUN , Seungkeun YOON
Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.
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公开(公告)号：US20250013856A1
公开(公告)日：2025-01-09
申请号：US18640853
申请日：2024-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Min Young MUN , Seok Ju YUN , Sei Joon KIM , Sang Joon KIM
IPC: G06N3/0464
Abstract: A convolutional neural network (CNN)-based analog in-sensor computing device may include a convolution layer including one or more convolution blocks configured to be used a predetermined number of times or more and perform a convolution operation, and an memory configured to temporarily store an output of the convolution layer and provide the stored analog output to a subsequent convolution layer.
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公开(公告)号：US20240069867A1
公开(公告)日：2024-02-29
申请号：US18351039
申请日：2023-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Ju YUN , Jaehyuk LEE , Seungchul JUNG , Soon-Wan KWON , Sungmeen MYUNG , Daekun YOON , Dong-Jin CHANG
CPC classification number: G06F7/523 , G06F7/501 , G06F7/5443 , G11C7/109
Abstract: An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.
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公开(公告)号：US20210409072A1
公开(公告)日：2021-12-30
申请号：US17474100
申请日：2021-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Ju YUN , Sang Joon KIM , Joonseong KANG
IPC: H04B5/00
Abstract: A wireless communication apparatus may include: an oscillator including a coil assembly exposed to an outside of the wireless communication apparatus, a variable capacitor, and a negative resistor; and a phase locking circuit connected to the coil assembly and the negative resistor. The phase locking circuit may be configured to generate a control signal to lock an oscillation frequency of the oscillator based on an oscillation signal generated by the oscillator, and provide the generated control signal to the variable capacitor.
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公开(公告)号：US20190052492A1
公开(公告)日：2019-02-14
申请号：US16058263
申请日：2018-08-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Ju YUN , Sang Joon KIM
Abstract: A receiver includes an antenna configured to receive a radio signal, a pulse generator configured to generate a pulse, an oscillator configured to be driven based on the pulse to generate an oscillation signal based on the radio signal, and a measurer configured to be driven by the pulse to measure an oscillation degree of the oscillation signal, wherein the radio signal is received based on the oscillation degree of the oscillation signal.
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Patent Agency Ranking
公开(公告)号：US20180309406A1
公开(公告)日：2018-10-25
申请号：US15838971
申请日：2017-12-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok Ju YUN
IPC: H03B5/12
CPC classification number: H04B1/0475 , H03B5/1215 , H03B5/1228 , H03B5/124 , H03F1/3211 , H03F3/45179 , H04B1/40
Abstract: A wireless communication apparatus includes an oscillator circuit configured to generate an oscillation signal corresponding to an oscillation frequency determined by an antenna, and a bias generator circuit configured to reconfigure an operation region mode of a transistor included in the oscillator circuit by adjusting a bias signal in response to an enable signal.
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17.发明申请公开(公告)号：US20140240191A1
公开(公告)日：2014-08-28
申请号：US14186553
申请日：2014-02-21
Applicant: SNU R&DB FOUNDATION , SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Sup LEE , Seong Joong KIM , Seok Ju YUN , Sang Wook NAM , Su Min YUN
IPC: H01Q1/50
CPC classification number: H01Q13/18
Abstract: An antenna is described including a slot formed in a cavity, a substrate configured to cover a portion of the cavity and the slot, and a first port and a second port configured to supply power to the antenna using a first feeding line and a second feeding line. Each of the feeding line and the second feeding line is connected to the slot in a vertical direction and disposed to be separate from one another. A first input impedance of the antenna from the first port differs from a second input impedance of the antenna from the second port.
Abstract translation: 描述了一种天线，其包括形成在空腔中的槽，构造成覆盖腔和槽的一部分的衬底以及被配置为使用第一馈电线和第二馈电来向天线供电的第一端口和第二端口 线。 馈送线和第二馈电线中的每一根在垂直方向上连接到槽，并且彼此分离设置。 来自第一端口的天线的第一输入阻抗与天线的第二输入阻抗与第二端口不同。
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公开(公告)号：US20240086153A1
公开(公告)日：2024-03-14
申请号：US18467521
申请日：2023-09-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungmeen MYUNG , Dong-Jin CHANG , Jaehyuk LEE , Daekun YOON , Seok Ju YUN
CPC classification number: G06F7/5443 , G06F7/405
Abstract: A multi-bit accumulator includes 1-bit Wallace trees each configured to perform an add operation on single-bit input data, tristate logic circuits each configured to output a result of the add operation of the 1-bit Wallace trees according to an enable signal provided to the tristate logic circuits, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the 1-bit Wallace trees by a shift operation based on a clock signal.
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公开(公告)号：US20240071548A1
公开(公告)日：2024-02-29
申请号：US18091258
申请日：2022-12-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungmeen MYUNG , Seok Ju YUN , Jaehyuk LEE , Seungchul JUNG
CPC classification number: G11C29/36 , G11C29/44 , G11C29/785 , G11C2029/3602
Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.
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公开(公告)号：US20240061649A1
公开(公告)日：2024-02-22
申请号：US18306686
申请日：2023-04-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Soon-Wan KWON , Seok Ju YUN , Seungchul JUNG
CPC classification number: G06F7/5443 , G06F7/5277 , G11C7/1069
Abstract: An in-memory computing (IMC) processor includes IMC macros, and includes a static random access memory (SRAM) IMC device including the plurality of IMC macros, and configured to perform a multiply and accumulate (MAC) operation between input data and first weight data of a first weight map applied to a first of IMC macros in a first direction in which an input feature map including the input data is written to the first IMC macro, and a two-dimensional (2D) shift accumulator configured to perform a shift operation on partial sums corresponding to respective MAC operation results of the IMC macros and accumulate a result of the shift operation.
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