公开(公告)号：US20210225425A1

公开(公告)日：2021-07-22

申请号：US17038488

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/406 ,  G11C5/06

Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

公开(公告)号：US10748634B2

公开(公告)日：2020-08-18

申请号：US16417834

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Ho Kim ,  Jihwan Yu ,  Seunghyun Cho

IPC: G11C19/28 ,  H01L27/11578 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  G11C5/02

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

公开(公告)号：US10354740B2

公开(公告)日：2019-07-16

申请号：US15842029

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Ho Kim ,  Jihwan Yu ,  Seunghyun Cho

IPC: G11C19/28 ,  H01L27/11578 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  G11C5/02

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

公开(公告)号：US20250038064A1

公开(公告)日：2025-01-30

申请号：US18444477

申请日：2024-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minwoo Cho ,  Seunghyun Cho

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498

Abstract: The present disclosure relates to chip-on-film packages. An example chip-on-film package comprises a base film including a first surface and a second surface opposite to the first surface. The base film includes a protection layer adjacent to the first surface, a film substrate adjacent to the second surface, a plurality of lead lines between the film substrate and the protection layer, and a bonding layer between the plurality of lead lines and the protection layer. The chip-on-film package includes a semiconductor chip adjacent to the first surface, and a mold layer that covers a top surface and a lateral surface of the semiconductor chip. The first surface includes a circuit surface on which the semiconductor chip is disposed and a thermal conductive surface that faces the circuit surface when the base film is bent. The thermal conductive surface is in direct contact with a top surface of the mold layer.

公开(公告)号：US20250022998A1

公开(公告)日：2025-01-16

申请号：US18583947

申请日：2024-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Cho ,  Jaemin Jung ,  Jeongkyu Ha

IPC: H01L33/62 ,  H01L25/075 ,  H01L25/16 ,  H01L33/48

Abstract: A film package includes a film substrate, vias penetrating through the film substrate, interconnection patterns on the film substrate, and a semiconductor chip electrically connected to at least one of the interconnection patterns and to the vias, wherein the interconnection patterns include input patterns, first output patterns, and second output patterns, the film package includes input pads on a surface of the film substrate, and the input patterns extend from the input pads, the film package includes first output pads positioned toward a first edge of the film substrate on a first surface of the film substrate, and the first output patterns extend from the first output pads, and the film package includes second output pads positioned toward a second edge of the film substrate on a second surface of the film substrate opposite to the first surface, and the second output patterns extend from the second output pads.

公开(公告)号：US20240204009A1

公开(公告)日：2024-06-20

申请号：US18237013

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Cho ,  Jaemin Jung ,  Jeongkyu Ha

IPC: H01L27/12

CPC classification number: H01L27/1244

Abstract: A film package includes: a film substrate having a first side surface and a second side surface opposing each other in a first direction, each of the first side surface and the second side surface extending in a second direction perpendicular to the first direction; at least one semiconductor chip disposed on the film substrate and extending lengthwise in the first direction; input terminals arranged on the film substrate along the first side surface, output terminals arranged on the film substrate along the second side surface, and wirings formed on the film substrate and electrically connecting the input terminals and the output terminals to the at least one semiconductor chip; and a protective layer covering the wirings on the film substrate.

公开(公告)号：US11960249B2

公开(公告)日：2024-04-16

申请号：US17708295

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taegyun Kim ,  Junghyun Kang ,  Kijung Kim ,  Shinhun Moon ,  Seunghyun Cho ,  Seongho Hong

IPC: G04G19/00 ,  A61B5/00 ,  A61B5/024 ,  G04G9/00 ,  G04G21/02 ,  H02J7/00 ,  H02J50/00 ,  H02J50/10 ,  H05K1/02 ,  H05K5/00

CPC classification number: G04G19/00 ,  G04G9/007 ,  G04G21/025 ,  H02J7/0042 ,  H02J50/005 ,  H05K1/028 ,  H05K5/0026 ,  A61B5/02416 ,  A61B5/681 ,  H02J50/10 ,  H05K2201/10106 ,  H05K2201/10151

Abstract: A wearable electronic device, for example a smart watch, has an optical sensor module disposed near a side of the device meant to face the wearer. The device also includes a wireless charging module. The optical sensor and wireless charging modules are at least partially integrated together via a flexible printed circuit board (“FPCB”) which is connected to both modules. The wireless charging module surrounds the FPCB of the optical sensor module, thus allowing a reduction in thickness of the wearable device and further allowing simplification in a process of assembly of the device.

公开(公告)号：US20240096909A1

公开(公告)日：2024-03-21

申请号：US18200609

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Cho ,  Jaemin Jung ,  Jeongkyu Ha

IPC: H01L27/12 ,  H05K7/20

CPC classification number: H01L27/1244 ,  H05K7/20954

Abstract: A chip on film (COF) package includes a film substrate including a base film having a mounting region, a main line pattern extending on the base film, and a branch line pattern extending on the base film and electrically connected to the main line pattern, a semiconductor chip vertically overlapping the mounting region, a first bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the main line pattern, and a second bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the branch line pattern, the branch line pattern extends so as not to overlap a first edge of the first bump structure facing a first edge of the mounting region and a first edge of the second bump structure facing the first edge of the mounting region.

公开(公告)号：US11559239B2

公开(公告)日：2023-01-24

申请号：US16860354

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： June Lee ,  Junhui Lee ,  Yongyi Kim ,  Seunghyun Cho

IPC: H05K1/18 ,  H01H13/52 ,  H01H13/14 ,  H01H13/04 ,  A61B5/332 ,  A61B5/00 ,  A61B5/282 ,  A61B5/339

Abstract: An electronic device is provided. The electronic device includes a housing, a printed circuit board disposed inside the housing and including a first face and a second face that faces away from the first face, a connection member disposed on the first face and electrically connected to the printed circuit board, a switch member disposed on the first face and at least partially overlaps the connection member when viewed from above the first face, and a button member including an electrically conductive member, and disposed to be capable of operating the switch member. The electrically conductive member is electrically connected to the connection member.