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公开(公告)号：US11669393B2
公开(公告)日：2023-06-06
申请号：US17495632
申请日：2021-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Youngkwang Yoo , Younggeun Lee , Yena Lee
CPC classification number: G06F11/1044 , G06F9/30029 , G06F9/544 , G06F11/3037 , G06F12/0246 , G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.
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2.发明授权公开(公告)号：US11537471B2
公开(公告)日：2022-12-27
申请号：US17469377
申请日：2021-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Eunchu Oh , Youngkwang Yoo , Younggeun Lee
Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
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公开(公告)号：US20220383932A1
公开(公告)日：2022-12-01
申请号：US17819289
申请日：2022-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunggeun Do , Youngsik Kim , Gongheum Han , Sangyun Kim , Seunghyun Cho
IPC: G11C11/408 , G11C5/06 , G11C11/406 , G11C11/4074
Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.
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4.发明授权公开(公告)号：US11507460B2
公开(公告)日：2022-11-22
申请号：US17448995
申请日：2021-09-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Eunchu Oh , Youngkwang Yoo , Younggeun Lee
Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
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公开(公告)号：US11163638B2
公开(公告)日：2021-11-02
申请号：US16695395
申请日：2019-11-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Youngkwang Yoo , Younggeun Lee , Yena Lee
Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.
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Patent Agency Ranking
公开(公告)号：US12198749B2
公开(公告)日：2025-01-14
申请号：US17819289
申请日：2022-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunggeun Do , Youngsik Kim , Gongheum Han , Sangyun Kim , Seunghyun Cho
IPC: G11C11/408 , G11C5/06 , G11C11/406 , G11C11/4074
Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.
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公开(公告)号：US10762000B2
公开(公告)日：2020-09-01
申请号：US15662072
申请日：2017-07-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mu-Tien Chang , Heehyun Nam , Youngsik Kim , Youngjin Cho , Dimin Niu , Hongzhong Zheng
IPC: G06F12/121 , G06F12/127 , G06F13/16 , G06F12/0868
Abstract: A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory, the method including assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines, assigning a validity score to each way based on a degree of validity of the cache line stored in each way, assigning an eviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way, and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.
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公开(公告)号：US10692834B2
公开(公告)日：2020-06-23
申请号：US15853170
申请日：2017-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsik Kim , Doojin Kim , Seokho Lee , Younggon Hwang
Abstract: A method for replacing a capillary of a wire bonding apparatus that includes a holding unit that holds a capillary includes transferring a capillary replacing unit to the wire bonding apparatus by a mobile robot in response to receiving a capillary replacement start signal from the wire bonding apparatus, separating, by the capillary replacing unit, the capillary corresponding to the replacement signal from the wire bonding apparatus, and installing, by the capillary replacing unit, a new capillary in the wire bonding apparatus.
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公开(公告)号：US09727474B2
公开(公告)日：2017-08-08
申请号：US13966889
申请日：2013-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD. , INDUSTRY & ACADEMIC COOPERATION GROUP OF SEJONG UNIVERSITY
Inventor： Kwon Taek Kwon , Youngsik Kim , Woo Chan Park , Young Duke Seo , Sang Oak Woo , Seok Yoon Jung , Duk Ki Hong
IPC: G09G5/36 , G06F12/0875 , G06F12/0855
CPC classification number: G06F12/0875 , G06F12/0855
Abstract: A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.
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公开(公告)号：US11785709B2
公开(公告)日：2023-10-10
申请号：US17368906
申请日：2021-07-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwon Kim , Youngsik Kim , Chanyoul Park , Kisung Bae , Hongpyo Bae , Seunggil Jeon , Youngjun Cho
CPC classification number: H05K1/0243 , H04B1/38 , H05K1/111 , H05K5/0017 , H05K7/1427 , H05K2201/10053
Abstract: An electronic device includes a housing including a first plate, a second plate, and a side member including a first conductive member and a second conductive member which surround a space between the first plate and the second plate and are separated from each other by a slit, a support member interposed in a space between the first plate and the second plate, a PCB, a wireless communication circuit disposed on the PCB, a display, a connection part protruding toward an inner part of the housing from an area of the second conductive member that is adjacent to the slit, the connection part being electrically connected with the second conductive member, and a coupling member coupled to the connection part. The wireless communication circuit is configured to electrically connect the second conductive member and the connection part with an antenna circuit provided on the PCB.
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