公开(公告)号：US11810776B2

公开(公告)日：2023-11-07

申请号：US17021321

申请日：2020-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

公开(公告)号：US20180122486A1

公开(公告)日：2018-05-03

申请号：US15700324

申请日：2017-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkyu Choi ,  Seungjun Shin

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2245 ,  G11C2207/2254 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A training method for a memory device includes providing, at a memory controller, a clock signal to the memory device to synchronize a control signal at a reference time point of the clock signal. When the clock signal, such as a training clock signal, does not transition after the reference time point, a failure time point is found at which the memory device fails to sample the control signal at the reference time point, based on the clock signal and the control signal. A synchronization time point of the control signal may be set, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point. A sampler circuit may sample the control signal at an edge of a rising edge of the clock signal.

公开(公告)号：US11917822B2

公开(公告)日：2024-02-27

申请号：US17036997

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

公开(公告)号：US11621034B2

公开(公告)日：2023-04-04

申请号：US17376915

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10699770B2

公开(公告)日：2020-06-30

申请号：US16579994

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10529393B2

公开(公告)日：2020-01-07

申请号：US15649060

申请日：2017-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjun Shin ,  Tae Young Oh

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C29/00 ,  G11C29/02 ,  G11C7/20 ,  G11C7/04

Abstract: An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, a row decoder for receiving a row address and selecting a word line corresponding to the row address, a column decoder for receiving a column address and selecting a bit line corresponding to the column address, a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line, and a data output driver. The method includes setting a calibration code for a driver control code, to control an initial current strength of the data output driver, and changing the calibration code to change the driver control code during a read or write operation for the memory cell array.

公开(公告)号：US10460793B2

公开(公告)日：2019-10-29

申请号：US16278339

申请日：2019-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C8/18 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/408

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.