-
公开(公告)号：US11829614B2
公开(公告)日：2023-11-28
申请号：US17842981
申请日：2022-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeonggeol Song , Sungrae Kim , Kijun Lee , Myungkyu Lee , Eunae Lee , Sunghye Cho
CPC classification number: G06F3/0626 , G06F3/064 , G06F3/0679 , G06F11/1068
Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.
-
公开(公告)号：US11631448B1
公开(公告)日：2023-04-18
申请号：US17244466
申请日：2021-04-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eunae Lee , Sunghye Cho , Kijun Lee , Junjin Kong , Yeonggeol Song
IPC: G11C11/406 , G06F12/06
Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.
-
公开(公告)号：US20230037996A1
公开(公告)日：2023-02-09
申请号：US17718422
申请日：2022-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Myungkyu Lee , Kijun Lee , Sunghye Cho
Abstract: An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.
-
公开(公告)号：US11106535B2
公开(公告)日：2021-08-31
申请号：US16926000
申请日：2020-07-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunghye Cho , Kijun Lee , Yeonggeol Song , Sungrae Kim , Chanki Kim , Myungkyu Lee , Sanguhn Cha
Abstract: An error correction circuit includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page as a read codeword based on an externally provided address to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.
-
公开(公告)号：US10461890B2
公开(公告)日：2019-10-29
申请号：US15891265
申请日：2018-02-07
Inventor： Seok-Ki Ahn , Kyeongcheol Yang , Daeyeol Yang , Sunghye Cho
Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system for supporting higher data rates Beyond 4th-Generation (4G) communication systems such as Long Term Evolution (LTE). A method for operating a receiver in a wireless communication system may include: receiving a signal from a transmitter; performing Integer Forcing (IF) equalization on the received signal; determining a log LikeLihood Ratio (LLR) value of each bit by using a posteriori probability of each bit for the signal determined based on an equalization matrix and a likelihood value for the signal; and decoding the signal by using the LLR value.
-
Patent Agency Ranking
公开(公告)号：US12212339B2
公开(公告)日：2025-01-28
申请号：US17984430
申请日：2022-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myungkyu Lee , Kijun Lee , Sunghye Cho , Sungrae Kim
Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.
-
公开(公告)号：US12057184B2
公开(公告)日：2024-08-06
申请号：US18164100
申请日：2023-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunghye Cho , Kiheung Kim , Sungrae Kim , Junhyung Kim , Kijun Lee , Myungkyu Lee , Changyong Lee , Sanguhn Cha
IPC: G11C29/42 , G11C11/408 , G11C11/4091 , G11C29/44 , G11C29/12
CPC classification number: G11C29/42 , G11C11/4087 , G11C11/4091 , G11C29/4401 , G11C2029/1202 , G11C2029/1204
Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
-
公开(公告)号：US12020739B2
公开(公告)日：2024-06-25
申请号：US18138849
申请日：2023-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunghye Cho , Kijun Lee , Eunae Lee
IPC: G11C7/12 , G11C11/406 , G11C11/408 , G11C11/4091 , G11C7/10 , G11C8/10
CPC classification number: G11C11/406 , G11C7/12 , G11C11/40611 , G11C11/40622 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C7/1078 , G11C8/10
Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.
-
公开(公告)号：US11605441B1
公开(公告)日：2023-03-14
申请号：US17461380
申请日：2021-08-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunghye Cho , Kiheung Kim , Sungrae Kim , Junhyung Kim , Kijun Lee , Myungkyu Lee , Changyong Lee , Sanguhn Cha
IPC: G11C29/42 , G11C29/44 , G11C11/408 , G11C11/4091 , G11C29/12
Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
-
公开(公告)号：US20230004308A1
公开(公告)日：2023-01-05
申请号：US17704354
申请日：2022-03-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Sunghye Cho , Kijun Lee , Myungkyu Lee
IPC: G06F3/06
Abstract: In a method of operating a memory controller, a decoding status flag is received from a memory module including a plurality of data chips and at least one parity chip. Each of the plurality of data chips and the at least one parity chip may include an on-die error correction code (ECC) engine. The decoding status flag is generated by the on-die ECC engines. A first number and a second number may be obtained based on the decoding status flag. The first number represents a number of first chips including an uncorrectable error that is uncorrectable by the on-die ECC engine. The second number represents a number of second chips including a correctable error that is correctable by the on-die ECC engine. At least one of a plurality of decoding schemes is selected based on at least one of the first number and the second number. A system ECC engine may perform ECC decoding on at least one of the first chips and the second chips based on the selected decoding scheme.
-
-
-
-
-
-
-
-
-
Search Results
51
records
(took 0.034 seconds)
