公开(公告)号：US20240234525A9

公开(公告)日：2024-07-11

申请号：US18234596

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ki Park ,  Sung Hwan Kim ,  Wan Don Kim ,  Heung Seok Ryu

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device includes an active pattern extending in a first direction, a plurality of gate structures on the active pattern spaced in the first direction, and including a gate electrode extending in a second direction, a source/drain pattern between adjacent gate structures, a silicide mask pattern on the source/drain pattern, an upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode, a source/drain contact on the source/drain pattern connected to the source/drain pattern, and a contact silicide film between the source/drain contact and the source/drain pattern in contact with a bottom surface of the silicide mask pattern, wherein a height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than a height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern.

公开(公告)号：US11799004B2

公开(公告)日：2023-10-24

申请号：US17694759

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US20220059533A1

公开(公告)日：2022-02-24

申请号：US17219083

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SU YOUNG BAE ,  Jong Ho Park ,  Dong Soo Lee ,  Wan Don Kim

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes first and second active patterns disposed on a substrate, a field insulating film disposed between the first and second active patterns, a first gate structure intersecting the first active pattern, and a second gate structure intersecting the second active pattern, in which the first gate structure includes a first gate insulating film on the first active pattern, a first upper insertion film on the first gate insulating film, and a first upper conductive film on the first upper insertion film, and the second gate structure includes a second gate insulating film on the second active pattern, a second upper insertion film on the second gate insulating film, and a second upper conductive film on the second upper insertion film. Each of the first and second upper insertion films may include an aluminum nitride film. Each of the first and second upper conductive films may include aluminum.

公开(公告)号：US11949012B2

公开(公告)日：2024-04-02

申请号：US17114598

申请日：2020-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Ho Park ,  Wan Don Kim ,  Weon Hong Kim ,  Hyeon Jun Baek ,  Byoung Hoon Lee ,  Jeong Hyuk Yim ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/516

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

公开(公告)号：US20230163076A1

公开(公告)日：2023-05-25

申请号：US17885025

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Ki PARK ,  Yoon Tae Hwang ,  Wan Don Kim ,  Sung Hwan Kim ,  Tae Yeol Kim

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76895

Abstract: A semiconductor device includes a gate structure including a gate electrode on a substrate. A source/drain pattern is on the substrate and positioned on a side surface of the gate electrode. A source/drain contact is on the source/drain pattern. A first conductive pad is on the source/drain contact. A second conductive pad is on the gate structure. A via plug penetrates the first conductive pad and is connected to the source/drain contact. A gate contact penetrates the second conductive pad and is connected to the gate electrode. A portion of the via plug protrudes from the first conductive pad. A portion of the gate contact protrudes from the second conductive pad. A height from an upper surface of the gate structure to an upper surface of the via plug is equal to a height from the upper surface of the gate structure to an upper surface of the gate contact.

公开(公告)号：US20220208679A1

公开(公告)日：2022-06-30

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L23/48

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.

公开(公告)号：US20220199790A1

公开(公告)日：2022-06-23

申请号：US17694759

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok LEE ,  Dae Yong KIM ,  Wan Don Kim ,  Jeong Hyuk YIM ,  Won Keun CHUNG ,  Hyo Seok CHOI ,  Sang Jin HYUN

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US11282939B2

公开(公告)日：2022-03-22

申请号：US16269712

申请日：2019-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon Lee ,  Wan Don Kim ,  Jong Ho Park ,  Sang Jin Hyun

IPC: H01L29/51 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.