公开(公告)号：US20170271286A1

公开(公告)日：2017-09-21

申请号：US15407422

申请日：2017-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGBAE KIM

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05092 ,  H01L2224/05095 ,  H01L2224/05097 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/35 ,  H01L2924/351

Abstract: A semiconductor device includes a semiconductor substrate including a circuit layer disposed therein, a bonding pad disposed on the semiconductor substrate, the bonding pad being electrically connected to the circuit layer, and a metal layer electrically connected to the bonding pad. The metal layer includes a first via electrically connected to the bonding pad, the first via providing an electrical path between the metal layer and the circuit layer, and a second via protruding toward the semiconductor substrate, the second via supporting the metal layer on the semiconductor substrate.

公开(公告)号：US20150243353A1

公开(公告)日：2015-08-27

申请号：US14505523

申请日：2014-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGKYU LEE ,  YEONGTAEK LEE ,  YOUNGBAE KIM

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C11/5614 ,  G11C11/5685 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

Abstract: A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a corresponding compliance current, and then programming the memory cell to a reset state by pre-reading the variable resistance memory cell to determine its resistance and resetting the memory cell using a variable reset voltage determined in response to the determined resistance.

Abstract translation: 一种在非易失性存储器件中复位可变电阻存储单元的方法包括： 使用相应的顺应性电流将存储器单元编程为设定状态，然后通过预读可变电阻存储单元来确定其电阻并使用响应中确定的可变复位电压来复位存储单元来将存储单元编程为复位状态 到确定的阻力。

公开(公告)号：US20250046692A1

公开(公告)日：2025-02-06

申请号：US18582798

申请日：2024-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGBAE KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: A wiring substrate includes a first re-distribution layer, a second re-distribution layer on the first re-distribution layer, and a core portion between the first re-distribution layer and the second re-distribution layer, wherein the core portion includes a bottom surface disposed on a top surface of the first re-distribution layer, and a first intermediate surface disposed on the top surface of the first re-distribution layer, wherein a distance between the top surface of the first re-distribution layer and the core portion along the first intermediate surface, which is measured in a direction perpendicular to the top surface of the first re-distribution layer, increases as a distance from the bottom surface increases.

公开(公告)号：US20250022824A1

公开(公告)日：2025-01-16

申请号：US18416608

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGBAE KIM

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor layer including a surface which extends in a first direction; and a first connection pad provided on the surface of the first semiconductor; and a second semiconductor chip including a second semiconductor layer; and a second connection pad provided on a surface of the second semiconductor layer. The first connection pad is directly connected to the second connection pad and a ratio of a width of the second connection pad in the first direction to a width of the first connection pad in the first direction is less than or equal to 1.1 and greater than or equal to 0.5.

公开(公告)号：US20250006648A1

公开(公告)日：2025-01-02

申请号：US18420135

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGBAE KIM

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A wiring substrate may include a core portion, an upper peripheral portion on a top surface of the core portion, and a lower peripheral portion on a bottom surface of the core portion. The upper peripheral portion may include a bridge chip provided on the top surface of the core portion, upper insulating patterns provided on the top surface of the core portion to cover the bridge chip, and upper interconnection patterns in the upper insulating patterns. The lower peripheral portion may include a dummy structure on the bottom surface of the core portion, lower insulating patterns on the bottom surface of the core portion to cover the dummy structure, and lower interconnection patterns in the lower insulating patterns. A mean thermal expansion coefficient of the upper peripheral portion may be substantially equal to a mean thermal expansion coefficient of the lower peripheral portion.

公开(公告)号：US20240395650A1

公开(公告)日：2024-11-28

申请号：US18405534

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGBAE KIM

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H10B80/00

Abstract: A high bandwidth memory according to an exemplary embodiment may include a buffer die, a memory stack structure disposed on the buffer die and including a stack of a plurality of memory dies, one or more heat dissipation structures disposed on the buffer die, and horizontally adjacent to the memory stack structure, and a molding material disposed on the buffer die so as to encapsulate the memory stack and the one or more heat dissipation structures.

公开(公告)号：US20210104452A1

公开(公告)日：2021-04-08

申请号：US16872567

申请日：2020-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHLE-GE LEE ,  YOUNGBAE KIM ,  JI-YONG PARK

IPC: H01L23/498 ,  H05K1/11 ,  H01L29/768 ,  H01L23/31

Abstract: Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.

公开(公告)号：US20190325960A1

公开(公告)日：2019-10-24

申请号：US16458594

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGWOO KIM ,  BONG-SOO KIM ,  YOUNGBAE KIM ,  KIJAE HUR ,  GWANHYEOB KOH ,  HYEONGSUN HONG ,  YOOSANG HWANG

IPC: G11C14/00 ,  H01L45/00 ,  G11C5/02 ,  G11C13/00 ,  G11C11/00 ,  H01L23/528 ,  H01L27/24

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.