Digital microphone interface circuit for voice recognition and including the same

    公开(公告)号:US11538479B2

    公开(公告)日:2022-12-27

    申请号:US17130401

    申请日:2020-12-22

    Abstract: Disclosed is an electronic device which includes an audio processing block for voice recognition in a low-power mode. The electronic device includes a digital microphone that receives a voice signal from a user and converts the received voice signal into a PDM signal, and a DMIC interface circuit. The DMIC interface circuit includes a PDM-PCM converting block that converts the PDM signal into a PCM signal, a maxscale gain tuning block that tunes a maxscale gain of the PCM signal received from the PDM-PCM converting block based on a distance information indicating a physical distance between the user and the electronic device acquired in advance of the converting of the PDM signal, and an anti-aliasing block that performs filtering for acquiring voice data of a target frequency band associated with a PCM signal output from the maxscale gain tuning block.

    Random number generators and methods of generating random numbers using adjustable meta-stable voltage

    公开(公告)号:US10101968B2

    公开(公告)日:2018-10-16

    申请号:US15634276

    申请日:2017-06-27

    Abstract: A random number generator may include a first meta-stable inverter having an input terminal and an output terminal connected to each other and configured to generate a meta-stable voltage, an amplifier configured to amplify the meta-stable voltage, control circuitry configured to adjust a threshold voltage of the meta-stable voltage, and a sampler configured to generate a random number based on sampling the meta-stable voltage. The random number generator may be configured to be operated according to different modes of operation of a plurality of modes of operation. The amplifier may be a second meta-stable inverter configured to amplify the meta-stable voltage or include an input terminal and an output terminal that are connected to each other based on the random number generator being operated according to a first mode of operation or a second mode of operation, respectively, of the plurality of modes of operation.

    Modular multiplier and modular multiplication method thereof
    16.
    发明授权
    Modular multiplier and modular multiplication method thereof 有权
    模块化乘法器及其乘法方法

    公开(公告)号:US09448768B2

    公开(公告)日:2016-09-20

    申请号:US13792642

    申请日:2013-03-11

    CPC classification number: G06F7/722 G06F7/728

    Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.

    Abstract translation: 提供了一种模数乘法器和一种模乘法。 模数乘法器包括:第一寄存器,其存储在先前周期计算的先前累积值; 存储在前一周期计算的先前商的第二寄存器; 商产生器,其使用从所述第一寄存器输出的存储的先前累积值生成商; 以及累加器,其接收操作数,乘数的位值,存储的先前累积值和存储的先前商,以计算当前周期中的累积值,其中计算的累加值被更新为第一寄存器,并且 生成商被更新到第二个寄存器。

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