公开(公告)号：US20240284658A1

公开(公告)日：2024-08-22

申请号：US18381248

申请日：2023-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyung KANG ,  Seohee PARK ,  Yong-Suk TAK ,  Joonnyung HEO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315 ,  H10B12/485

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same, and the semiconductor device according to an embodiment includes: a substrate including an active region defined by an element isolation layer; a word line crossing the active region; a bit line crossing the active region in a direction different from the word line; a direct contact connecting between the active region and the bit line; a buried contact connected to the active region; and a bit line spacer that is disposed between the bit line and the buried contact and includes carbon. The bit line spacer includes a first region that is adjacent to the bit line and has a first carbon content and a second region that is adjacent to the buried contact and has a second carbon content that is higher than the first carbon content.

公开(公告)号：US20170200718A1

公开(公告)日：2017-07-13

申请号：US15384834

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hyun CHOI ,  Yong-Suk TAK ,  Gi-Gwan PARK ,  Bon-Young KOO ,  Ki-Yeon PARK ,  Won-Oh SEO

IPC: H01L27/088 ,  H01L29/08 ,  H01L23/26 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L27/0886 ,  H01L21/02636 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L23/26 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.

公开(公告)号：US20170103916A1

公开(公告)日：2017-04-13

申请号：US15182024

申请日：2016-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ho JEON ,  Sang-Su KIM ,  Cheol KIM ,  Yong-Suk TAK ,  Myung-Geun SONG ,  Gi-Gwan PARK

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/49 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.