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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    11.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210296397A1

    公开(公告)日：2021-09-23

    申请号：US17019641

    申请日：2020-09-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung Pil KO ,  Yongjae KIM

    IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

    Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.

    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND EMBEDDED DEVICE
    12.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND EMBEDDED DEVICE 有权

    公开(公告)号：US20210151502A1

    公开(公告)日：2021-05-20

    申请号：US16892583

    申请日：2020-06-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin KIM ,  Yongjae KIM ,  Kilho LEE

    IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02

    Abstract: A magnetoresistive random access memory device including a first insulating interlayer on a substrate; lower electrode contacts passing through the first insulating interlayer; first structures on the lower electrode contacts, respectively, each of the first structures including a stacked lower electrode, magnetic tunnel junction (MTJ) structure, and upper electrode; a second insulating interlayer on the first structures and the first insulating interlayer, the second insulating interlayer filling a space between the first structures; a third insulating interlayer directly contacting the second insulating interlayer, the third insulating interlayer having a dielectric constant lower than a dielectric constant of the second insulating interlayer; and a bit line passing through the third insulating interlayer and the second insulating interlayer, the bit line contacting the upper electrode of one of the first structures.

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