中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.021 seconds)

    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME
    13.
    发明申请
    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220075541A1

    公开(公告)日：2022-03-10

    申请号：US17335307

    申请日：2021-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

    IPC: G06F3/06 ,  H01L25/18 ,  G11C7/10 ,  G11C7/22

    Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME
    15.
    发明申请
    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20230138048A1

    公开(公告)日：2023-05-04

    申请号：US18145186

    申请日：2022-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

    IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

    Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

    Memory device for supporting new command input scheme and method of operating the same
    16.
    发明授权
    Memory device for supporting new command input scheme and method of operating the same 有权

    公开(公告)号：US11636885B2

    公开(公告)日：2023-04-25

    申请号：US17574174

    申请日：2022-01-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device
    18.
    发明授权
    Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device 有权

    公开(公告)号：US11416178B2

    公开(公告)日：2022-08-16

    申请号：US17014667

    申请日：2020-09-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsung Shin ,  Sanghyuk Kwon ,  Youngcheon Kwon ,  Sukhan Lee ,  Haesuk Lee

    IPC: G06F3/06 ,  G06N3/02

    Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

    Semiconductor memory devices and memory systems
    19.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11170868B2

    公开(公告)日：2021-11-09

    申请号：US16864787

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin Ryu ,  Sanguhn Cha ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Youngcheon Kwon ,  Jaeyoun Youn

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/14 ,  G11C7/10 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

Patent Agency Ranking