公开(公告)号：US11195954B2

公开(公告)日：2021-12-07

申请号：US16732864

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

公开(公告)号：US20200381563A1

公开(公告)日：2020-12-03

申请号：US16734537

申请日：2020-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Kihwan Kim ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

公开(公告)号：US20200381562A1

公开(公告)日：2020-12-03

申请号：US16715431

申请日：2019-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Junbeom Park ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

公开(公告)号：US20190252526A1

公开(公告)日：2019-08-15

申请号：US16116577

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo ,  Jeongho Yoo ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device includes a well region in a substrate, a semiconductor pattern on the well region, the semiconductor pattern including an impurity, and a gate electrode on the semiconductor pattern. A concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region.

公开(公告)号：US12132119B2

公开(公告)日：2024-10-29

申请号：US17489181

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan Kim ,  Sunguk Jang ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.

公开(公告)号：US12051722B2

公开(公告)日：2024-07-30

申请号：US18205671

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin Jung ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1037 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US11699613B2

公开(公告)日：2023-07-11

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon Kim ,  Seung Hun Lee ,  Yang Xu ,  Jeongho Yoo ,  Jongryeol Yoo ,  Youngdae Cho

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/762 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02225 ,  H01L21/2253 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/42316 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/7848

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

公开(公告)号：US11670680B2

公开(公告)日：2023-06-06

申请号：US17559347

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin Jung ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/1037 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US11417776B2

公开(公告)日：2022-08-16

申请号：US16715431

申请日：2019-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Junbeom Park ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

公开(公告)号：US20220085202A1

公开(公告)日：2022-03-17

申请号：US17533499

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.