公开(公告)号：US09525042B2

公开(公告)日：2016-12-20

申请号：US14700346

申请日：2015-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/28 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

公开(公告)号：US09397013B2

公开(公告)日：2016-07-19

申请号：US14854528

申请日：2015-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chongkwang Chang ,  Sungwoo Kang ,  Chunghowan Kim ,  Youngmook Oh ,  Seobum Lee ,  Gahyun Lim

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/308

CPC classification number: H01L22/20 ,  H01L21/3085 ,  H01L22/12 ,  H01L27/1104

Abstract: A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.

Abstract translation: 一种控制用于形成半导体器件精细图案的蚀刻工艺的方法包括在衬底上形成具有多个开口的下部图案，获得下部图案的宽度值，以及控制用于形成 使用宽度值降低图案。

公开(公告)号：US09064723B2

公开(公告)日：2015-06-23

申请号：US13751731

申请日：2013-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/788 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。

公开(公告)号：US11869811B2

公开(公告)日：2024-01-09

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/0886

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20190244965A1

公开(公告)日：2019-08-08

申请号：US16386407

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1108 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/785

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US10366927B2

公开(公告)日：2019-07-30

申请号：US15405420

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US10332779B2

公开(公告)日：2019-06-25

申请号：US15342456

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok Min ,  Moojin Kim ,  Seongjin Nam ,  Sughyun Sung ,  YoungHoon Song ,  Youngmook Oh

IPC: H01L21/02 ,  H01L21/762 ,  H01L27/108 ,  H01L21/3065 ,  H01L21/311

Abstract: A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device isolation layer to fill the trenches, and removing an upper portion of the device isolation layer to expose an upper side surface of the fin structure. The exposing of the upper side surface of the fin structure may include repeatedly performing an etching cycle including a first step and a second step, and an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step.

公开(公告)号：US09911659B2

公开(公告)日：2018-03-06

申请号：US15189312

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Woong Lee ,  Hanseung Kwak ,  Youngmook Oh

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/0649

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.

公开(公告)号：US20150311310A1

公开(公告)日：2015-10-29

申请号：US14700346

申请日：2015-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOKJUN WON ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。

公开(公告)号：US20130299916A1

公开(公告)日：2013-11-14

申请号：US13751731

申请日：2013-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L27/088

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.