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公开(公告)号：US20220399054A1
公开(公告)日：2022-12-15
申请号：US17840779
申请日：2022-06-15
Applicant: Seagate Technology LLC
Inventor： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
Abstract: A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).
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公开(公告)号：US20220328086A1
公开(公告)日：2022-10-13
申请号：US17719637
申请日：2022-04-13
Applicant: Seagate Technology LLC
Inventor： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
IPC: G11C11/22 , H01L27/1159 , H01L27/11597
Abstract: A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.
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Patent Agency Ranking
公开(公告)号：US12112821B2
公开(公告)日：2024-10-08
申请号：US17845643
申请日：2022-06-21
Applicant: Seagate Technology LLC
Inventor： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
CPC classification number: G11C29/4401 , G11C16/3495 , G11C29/1201 , G11C29/46
Abstract: A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.
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公开(公告)号：US11899590B2
公开(公告)日：2024-02-13
申请号：US17844141
申请日：2022-06-20
Applicant: Seagate Technology LLC
Inventor： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
IPC: G06F12/08 , G06F12/0891 , G06F12/0895 , G06F12/1027
CPC classification number: G06F12/0891 , G06F12/0895 , G06F12/1027 , G06F2212/60
Abstract: A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.
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公开(公告)号：US11853213B2
公开(公告)日：2023-12-26
申请号：US17730920
申请日：2022-04-27
Applicant: Seagate Technology LLC
Inventor： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
IPC: G06F12/0802 , G06F3/06
CPC classification number: G06F12/0802 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F2212/60
Abstract: Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.
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公开(公告)号：US20220405003A1
公开(公告)日：2022-12-22
申请号：US17841083
申请日：2022-06-15
Applicant: Seagate Technology LLC
Inventor： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
IPC: G06F3/06
Abstract: Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).
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公开(公告)号：US20220404982A1
公开(公告)日：2022-12-22
申请号：US17844174
申请日：2022-06-20
Applicant: Seagate Technology LLC
Inventor： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
Abstract: A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.
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