-
公开(公告)号：US10254969B2
公开(公告)日：2019-04-09
申请号：US15154786
申请日：2016-05-13
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Ryan J. Goss , Antoine Khoueir , Ara Patapoutian
Abstract: Systems and methods for improving data refresh in flash memory are described. In one embodiment, the method includes identifying a first garbage collection unit (GCU) of the storage system, computing a parity function in relation to the first GCU, identifying a data impairment in a first block, the first block being from the N blocks in the first GCU, removing the first block from the first GCU after identifying the data impairment in the first block, and recomputing the parity function when the first block is not cloned.
-
公开(公告)号：US09910606B2
公开(公告)日：2018-03-06
申请号：US15078151
申请日：2016-03-23
Applicant: Seagate Technology LLC
Inventor： Antoine Khoueir , Ara Patapoutian , David S. Ebsen , Ryan J. Goss
CPC classification number: G06F3/0616 , G06F3/0649 , G06F3/0653 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G11C16/349 , G11C29/42 , G11C29/4401 , G11C29/52
Abstract: Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.
-
公开(公告)号：US10289305B2
公开(公告)日：2019-05-14
申请号：US15971871
申请日：2018-05-04
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Dana L. Simonson , Kristofer C. Conklin , Ryan J. Goss , Robert W. Moss , Stacey Secatch
Abstract: Systems and methods for enhanced read recovery based on write time information are described. In one embodiment, the systems and methods include opening a block of flash memory cells for programming, tracking a block open time, and performing a read operation of a programmed page from the block based at least in part on the block open time. In some embodiments, the block includes a plurality of pages, each page including a plurality of flash memory cells. In some cases, the block open time includes an amount of time between the block opening for programming to a time the block closes for programming.
-
公开(公告)号：US10229052B2
公开(公告)日：2019-03-12
申请号：US15609198
申请日：2017-05-31
Applicant: Seagate Technology, LLC
Inventor： Timothy Canepa , Ryan J. Goss , Stephen Hanna
Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.
-
公开(公告)号：US10126964B2
公开(公告)日：2018-11-13
申请号：US15605442
申请日：2017-05-25
Applicant: Seagate Technology LLC
Inventor： Jeffrey Munsil , Jackson Ellis , Ryan J. Goss
IPC: G06F12/00 , G06F3/06 , G06F12/0873 , G06F12/0811
Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.
-
Patent Agency Ranking
公开(公告)号：US20220115076A1
公开(公告)日：2022-04-14
申请号：US17499418
申请日：2021-10-12
Applicant: Seagate Technology LLC
Inventor： Ryan J. Goss , Christopher A. Smith , Indrajit Zagade , Jonathan Henze
Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.
-
公开(公告)号：US20220027234A1
公开(公告)日：2022-01-27
申请号：US17380655
申请日：2021-07-20
Applicant: Seagate Technology LLC
Inventor： Ryan J. Goss , Jack V. Anderson , Jonathan M. Henze
Abstract: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.
-
公开(公告)号：US10896002B2
公开(公告)日：2021-01-19
申请号：US16212200
申请日：2018-12-06
Applicant: Seagate Technology LLC
Inventor： Benjamin J. Scott , Steven S. Williams , Stephen H. Perlmutter , Ryan J. Goss , Daniel J. Benjamin
Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). In some embodiments, a write stream is formed of user data blocks to be sequentially written to a non-volatile memory (NVM). An entry of a reverse directory footer is generated for each user data block in the write stream to describe a physical address in the NVM at which the corresponding user data block is to be stored. The entries are accumulated in a buffer memory until the total count of entries reaches a predetermined threshold and a complete footer data structure is formed. The complete footer data structure is thereafter inserted into the write stream for writing, with the data blocks, to the NVM. The complete footer data structure has an overall size that corresponds to an overall size of each of the user data blocks.
-
公开(公告)号：US20200004461A1
公开(公告)日：2020-01-02
申请号：US16212200
申请日：2018-12-06
Applicant: Seagate Technology LLC
Inventor： Benjamin J. Scott , Steven S. Williams , Stephen H. Perimutter , Ryan J. Goss , Daniel J. Benjamin
Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). In some embodiments, a write stream is formed of user data blocks to be sequentially written to a non-volatile memory (NVM). An entry of a reverse directory footer is generated for each user data block in the write stream to describe a physical address in the NVM at which the corresponding user data block is to be stored. The entries are accumulated in a buffer memory until the total count of entries reaches a predetermined threshold and a complete footer data structure is formed. The complete footer data structure is thereafter inserted into the write stream for writing, with the data blocks, to the NVM. The complete footer data structure has an overall size that corresponds to an overall size of each of the user data blocks.
-
公开(公告)号：US20180275899A1
公开(公告)日：2018-09-27
申请号：US15605442
申请日：2017-05-25
Applicant: Seagate Technology LLC
Inventor： Jeffrey Munsil , Jackson Ellis , Ryan J. Goss
IPC: G06F3/06 , G06F12/0873 , G06F12/0811
CPC classification number: G06F3/0619 , G06F3/065 , G06F3/0659 , G06F3/0688 , G06F12/0811 , G06F12/0873 , G06F2212/283
Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.
-
-
-
-
-
-
-
-
-
Search Results
25
records
(took 0.014 seconds)
