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公开(公告)号：US10290358B2
公开(公告)日：2019-05-14
申请号：US15639052
申请日：2017-06-30
Applicant: Seagate Technology LLC
Abstract: Read threshold voltage tracking techniques are provided for multiple dependent read threshold voltages using syndrome weights. One method comprises reading codewords of multiple pages using different first read threshold voltages and a default second read threshold voltage; decoding read values for the multiple pages for the different first read threshold voltages and the default second read threshold voltage; aggregating a syndrome weight for each failed decoding attempt for the different first read threshold voltages; identifying a selected first read threshold voltage using a corresponding syndrome weight; reading codewords of the multiple pages using the selected first read threshold voltage and different second read threshold voltages; decoding read values for the selected first read threshold voltage and the different second read threshold voltages; aggregating the syndrome weight for the different second read threshold voltages; and identifying a selected second read threshold voltage using a corresponding syndrome weight.
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12.发明申请公开(公告)号：US20190130966A1
公开(公告)日：2019-05-02
申请号：US15799484
申请日：2017-10-31
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time; shift the plurality of read reference voltages using the at least one reference voltage offset; and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after a predefined time interval since a programming of the multi-level memory cells.
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13.发明申请公开(公告)号：US20190122726A1
公开(公告)日：2019-04-25
申请号：US16217883
申请日：2018-12-12
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
CPC classification number: G11C11/5642 , G11C7/14 , G11C16/28 , G11C2211/5632 , G11C2211/5634
Abstract: Techniques are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages using binary data from the memory, wherein the gap is estimated using statistical characteristics of at least one of two adjacent memory levels of the memory; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels and the gap; and updating the read threshold voltage with the adjusted read threshold voltage. Pages of the memory are optionally read at multiple read threshold offset locations to obtain disparity statistics, which can be used to estimate mean and/or standard deviation values for a given memory level. The gap is optionally estimated using the mean and/or standard deviation values.
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14.发明授权公开(公告)号：US10192614B2
公开(公告)日：2019-01-29
申请号：US14962538
申请日：2015-12-08
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages; determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels, a distribution of data values read from one or more cells using a plurality of read threshold voltages and the gap; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage with the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.
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公开(公告)号：US10043582B2
公开(公告)日：2018-08-07
申请号：US15496498
申请日：2017-04-25
Applicant: Seagate Technology LLC
IPC: G11C16/26 , G11C16/34 , G11C29/50 , G06F11/10 , G11C7/10 , G11C11/56 , H03M13/11 , H03M13/37 , H03M13/00 , G11C16/10 , G06F11/00 , G11C16/16 , G11C16/04 , G11C16/28 , G06F12/02 , H03M13/05
Abstract: A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages. Once the predefined limit is reached, the following exemplary steps are performed: (i) mapping the readings to a corresponding likelihood value using different likelihood value assignments, and (ii) recording a syndrome weight for failed decoding attempts of the readings using the different likelihood value assignments; and using a given read threshold voltage and/or a likelihood value assignment associated with a substantially minimum syndrome weight as an initial read threshold voltage and/or a higher priority read threshold voltage for subsequent read retry operations.
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Patent Agency Ranking
16.发明授权公开(公告)号：US09898209B2
公开(公告)日：2018-02-20
申请号：US15480638
申请日：2017-04-06
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/061 , G06F3/0617 , G06F3/0653 , G06F3/0655 , G06F3/0679 , G06F3/0688
Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. The controller may be coupled to the memory and configured to process a plurality of read/write operations to/from the memory, store data in the plurality of memory devices using units of super-blocks, and generate a number of unique weight statistics in a single read operation by reading a number of dies within a super-block with dissimilar read reference voltages. Each super-block generally includes a block from a die of each of the plurality of memory devices. The controller may be further configured to split the number of dies in each super-block into two sets and collect page weights for upper pages from one of the two sets and page weights for lower pages from the other of the two sets.
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公开(公告)号：US09818488B2
公开(公告)日：2017-11-14
申请号：US14928284
申请日：2015-10-30
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , AbdelHakim Salem Alhussien , Zhengang Chen , Erich F. Haratsch
CPC classification number: G11C16/26 , G06F11/0727 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C11/5642 , G11C16/0483
Abstract: A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates.
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18.发明申请公开(公告)号：US20170212693A1
公开(公告)日：2017-07-27
申请号：US15480638
申请日：2017-04-06
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/061 , G06F3/0617 , G06F3/0653 , G06F3/0655 , G06F3/0679 , G06F3/0688
Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. The controller may be coupled to the memory and configured to process a plurality of read/write operations to/from the memory, store data in the plurality of memory devices using units of super-blocks, and generate a number of unique weight statistics in a single read operation by reading a number of dies within a super-block with dissimilar read reference voltages. Each super-block generally includes a block from a die of each of the plurality of memory devices. The controller may be further configured to split the number of dies in each super-block into two sets and collect page weights for upper pages from one of the two sets and page weights for lower pages from the other of the two sets.
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19.发明授权公开(公告)号：US09645763B2
公开(公告)日：2017-05-09
申请号：US14181893
申请日：2014-02-17
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/061 , G06F3/0617 , G06F3/0653 , G06F3/0655 , G06F3/0679 , G06F3/0688
Abstract: An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.
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公开(公告)号：US20170125111A1
公开(公告)日：2017-05-04
申请号：US14928284
申请日：2015-10-30
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , AbdelHakim Salem Alhussien , Zhengang Chen , Erich F. Haratsch
CPC classification number: G11C16/26 , G06F11/0727 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C11/5642 , G11C16/0483
Abstract: A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates.
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