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公开(公告)号:US10147501B1
公开(公告)日:2018-12-04
申请号:US15607784
申请日:2017-05-30
Applicant: Seagate Technology, LLC
Inventor: David S. Ebsen , Mark Ish , Timothy Canepa
IPC: G11C7/10 , G11C29/00 , G06F12/02 , G11C11/406 , G11C7/18 , G11C8/14 , G06F12/1045
CPC classification number: G11C29/789 , G06F12/0238 , G06F12/1054 , G06F12/1063 , G11C7/18 , G11C8/14 , G11C11/40607
Abstract: A data storage device may consist of a non-volatile memory connected to a selection module. The non-volatile memory can have a rewritable in-place memory cell that has a read-write asymmetry. The selection module can dedicate a portion of the non-volatile memory to a data map that can be self-contained along with reactively and proactively altered by the selection module.
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公开(公告)号:US10133681B2
公开(公告)日:2018-11-20
申请号:US15217863
申请日:2016-07-22
Applicant: SEAGATE TECHNOLOGY LLC
Inventor: Timothy Canepa , Ramdas Kachare
Abstract: Systems and methods for using encryption keys to manage data retention are described. In one embodiment, the systems and methods may include receiving data such as user data from a host of the storage drive, encrypting the data using an encryption key, writing the encrypted data to the storage drive, and retaining the encrypted data on the storage drive based at least in part on a validity of the encryption key.
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公开(公告)号:US10068663B1
公开(公告)日:2018-09-04
申请号:US15607801
申请日:2017-05-30
Applicant: Seagate Technology, LLC
Inventor: David S. Ebsen , Mark Ish , Timothy Canepa
Abstract: A non-volatile memory may be resident in a data storage device. The non-volatile memory can consist of a rewritable in-place memory cell having a read-write asymmetry. The non-volatile memory may be divided into a first group of tiers with a selection module of the data storage device prior to adapting to an event by altering the non-volatile memory into a second group of tiers. The first and second groups of tiers being different.
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公开(公告)号:US09934174B2
公开(公告)日:2018-04-03
申请号:US14858716
申请日:2015-09-18
Applicant: Seagate Technology LLC
Inventor: Ramdas Kachare , Timothy Canepa
CPC classification number: G06F13/28 , G06F13/1605 , G06F13/4022 , G06F13/4282
Abstract: An apparatus to arbitrate data transfer between a computing host and a storage device across an interface includes a data transfer limiter configured to track an amount of data credits used by a data transfer across the interface and an amount of accrued data credits available to the interface. The apparatus further includes a data transfer arbiter configured to selectively disable the data transfer across the interface when the amount of data credits used by the data transfer across the interface exceeds a first threshold, and to selectively enable the data transfer across the interface when the amount of data credits used by the data transfer across the interface does not exceed a second threshold. The amount of accrued data credits reduces the amount of data credits used by the data transfer.
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公开(公告)号:US20170083463A1
公开(公告)日:2017-03-23
申请号:US14858716
申请日:2015-09-18
Applicant: Seagate Technology LLC
Inventor: Ramdas Kachare , Timothy Canepa
CPC classification number: G06F13/28 , G06F13/1605 , G06F13/4022 , G06F13/4282
Abstract: Example techniques to selectively enable data transfer using accrued data credits are disclosed. In one aspects of the present disclosure, an apparatus to arbitrate data transfer between a computing host and a storage device across an interface comprises a data transfer limiter to track an amount of data credits used by a data transfer across the interface and an amount of accrued data credits available to the interface. The apparatus further comprises a data transfer arbiter to selectively disable the data transfer across the interface when the amount of data credits used by the data transfer across the interface exceeds a first threshold, and to selectively enable the data transfer across the interface when the amount of data credits used by the data transfer across the interface does not exceed a second threshold. The amount of accrued data credits reduces the amount of data credits used by the data transfer.
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公开(公告)号:US20160306577A1
公开(公告)日:2016-10-20
申请号:US15196363
申请日:2016-06-29
Applicant: Seagate Technology LLC
Inventor: Timothy Canepa , Leonid Baryudin , Stephen D. Hanna , Alex G. Tang
CPC classification number: G06F3/0619 , G06F3/0608 , G06F3/0613 , G06F3/064 , G06F3/0652 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F12/0246 , G06F12/0802 , G06F12/10 , G06F2212/1032 , G06F2212/1044 , G06F2212/214 , G06F2212/281 , G06F2212/312 , G06F2212/7205
Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.
Abstract translation: 一种装置包括存储器和控制器。 存储器可以被配置为存储数据。 控制器可以被配置为处理多个输入/输出请求以从/从存储器读/写。 控制器通常包括处理器,高速缓存和硬件辅助电路。 处理器可以被配置为通过生成起始索引来启动再循环操作。 缓存可以被配置为缓冲地图的第一级并且小于地图的所有第二级。 硬件辅助电路可以被配置为响应于开始索引来搜索高速缓存中的地图的第二级或第二级的任何部分,并且响应于搜索检测到存储器中的一个或多个块来通知处理器 包含有效数据要循环使用。
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公开(公告)号:US09405672B2
公开(公告)日:2016-08-02
申请号:US13941820
申请日:2013-07-15
Applicant: Seagate Technology LLC
Inventor: Timothy Canepa , Leonid Baryudin , Stephen D. Hanna , Alex G. Tang
IPC: G06F12/02
CPC classification number: G06F3/0619 , G06F3/0608 , G06F3/0613 , G06F3/064 , G06F3/0652 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F12/0246 , G06F12/0802 , G06F12/10 , G06F2212/1032 , G06F2212/1044 , G06F2212/214 , G06F2212/281 , G06F2212/312 , G06F2212/7205
Abstract: An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data.
Abstract translation: 公开了一种具有处理器和电路的装置。 处理器通常被配置为发起操作以循环非易失性存储器中的多个源块。 电路通常被配置为(i)搜索在映射中的多个级别中的第一级,所述映射定义在与计算机的接口处使用的多个逻辑地址和在存储器中使用的多个物理地址之间的多个翻译 以及(ii)响应于在第一级中检测到包含有效数据的一个或多个要被回收的源块的检测通知处理器。
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公开(公告)号:US10559376B2
公开(公告)日:2020-02-11
申请号:US16148409
申请日:2018-10-01
Applicant: Seagate Technology LLC
Inventor: Timothy Canepa , Mark Ish , David S. Ebsen
Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.
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公开(公告)号:US10430357B2
公开(公告)日:2019-10-01
申请号:US15899910
申请日:2018-02-20
Applicant: Seagate Technology LLC
Inventor: Ramdas Kachare , Timothy Canepa
Abstract: An apparatus to arbitrate data transfer between a computing host and a storage device across an interface includes a data transfer limiter configured to track an amount of data credits used by a data transfer across the interface and an amount of accrued data credits available to the interface. The apparatus further includes a data transfer arbiter configured to selectively disable the data transfer across the interface when the amount of data credits used by the data transfer across the interface exceeds a first threshold, and to selectively enable the data transfer across the interface when the amount of data credits used by the data transfer across the interface does not exceed a second threshold. The amount of accrued data credits reduces the amount of data credits used by the data transfer.
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公开(公告)号:US20190096506A1
公开(公告)日:2019-03-28
申请号:US16148409
申请日:2018-10-01
Applicant: Seagate Technology LLC
Inventor: Timothy Canepa , Mark Ish , David S. Ebsen
CPC classification number: G11C29/789 , G06F12/0238 , G06F12/08 , G06F12/0868 , G06F2212/1016 , G06F2212/211 , G06F2212/214 , G06F2212/7203 , G11C7/1006 , G11C7/1084 , G11C7/18 , G11C8/14 , G11C11/005 , G11C2207/102 , G11C2207/2245 , G11C2207/2272
Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.
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