公开(公告)号：US07190624B2

公开(公告)日：2007-03-13

申请号：US11141732

申请日：2005-05-31

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： C11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

摘要翻译： 根据本发明的闪速存储器件包括用作状态机的具有实现的擦除算法的擦除控制电路，其可以防止闪速存储器单元被过度擦除。 擦除控制电路首先检查所选择的单元的阈值电压是否达到比对应于擦除状态的目标阈值电压范围的最大值高的预定预验证电压。 当所选择的单元中的至少一个具有高于预验证电压的阈值电压时，高电压发生器产生逐步增加预定电压电平的体电压。 并且，当所选择的单元都具有等于或小于预验证电压的阈值电压时，高电压发生器产生恒定的体电压。 根据该体电压控制方案，在擦除操作时被擦除的闪存单元的数量减少，减少了总擦除时间。

公开(公告)号：US20050232022A1

公开(公告)日：2005-10-20

申请号：US11141732

申请日：2005-05-31

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C11/34 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

公开(公告)号：US06407944B1

公开(公告)日：2002-06-18

申请号：US09533306

申请日：2000-03-23

申请人： Ki-Hwan Choi ,  Jong-Min Park

发明人： Ki-Hwan Choi ,  Jong-Min Park

IPC分类号： G11C1606

CPC分类号： G11C16/107 ,  G11C16/3404

摘要： A method is disclosed for preventing over-erasure in a nonvolatile memory device having a plurality of sectors, each sector including a main field and a redundant field. The method includes the steps of programming memory cells included in the main and redundant fields, erasing the memory cells included in the main and redundant fields, and programming over-erased cells of the memory cells included in the main and redundant fields. The main and redundant fields are included in a sector.

摘要翻译： 公开了一种用于防止具有多个扇区的非易失性存储器件中的过度擦除的方法，每个扇区包括主场和冗余场。 该方法包括以下步骤：对包括在主场和冗余场中的存储单元进行编程，擦除包括在主场和冗余场中的存储单元，以及编程包括在主场和冗余场中的存储单元的过擦除单元。 主要和冗余领域包括在一个部门。

公开(公告)号：US06314027B1

公开(公告)日：2001-11-06

申请号：US09626172

申请日：2000-07-27

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C700

CPC分类号： G11C16/3468

摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

摘要翻译： 根据本发明的闪速存储器件包括用作状态机的具有实现的擦除算法的擦除控制电路，其可以防止闪速存储器单元被过度擦除。 擦除控制电路首先检查所选择的单元的阈值电压是否达到比对应于擦除状态的目标阈值电压范围的最大值高的预定预验证电压。 当所选择的单元中的至少一个具有高于预验证电压的阈值电压时，高电压发生器产生逐步增加预定电压电平的体电压。 并且，当所选择的单元都具有等于或小于预验证电压的阈值电压时，高电压发生器产生恒定的体电压。 根据该体电压控制方案，在擦除操作时被擦除的闪存单元的数量减少，减少了总擦除时间。

公开(公告)号：US6064596A

公开(公告)日：2000-05-16

申请号：US213722

申请日：1998-12-17

申请人： Ki-Hwan Choi ,  Jong-Min Park

发明人： Ki-Hwan Choi ,  Jong-Min Park

IPC分类号： G11C16/02 ,  G11C16/16 ,  G11C16/00

CPC分类号： G11C16/3445 ,  G11C16/16

摘要： An electrically erasable and programmable non-volatile semiconductor memory device and method of erasing the same device are provided. A fail bit counter is provided for the device and method. The fail bit counter counts erase fail bits during the sector erase operation. An erase control circuit selectively terminates the sector erase operation depending upon erase fail bit number.

摘要翻译： 提供了电可擦除和可编程的非易失性半导体存储器件以及擦除相同器件的方法。 为设备和方法提供故障位计数器。 故障位计数器在扇区擦除操作期间计数擦除失败位。 擦除控制电路根据擦除失败位数选择性地终止扇区擦除操作。

公开(公告)号：US08499210B2

公开(公告)日：2013-07-30

申请号：US12943369

申请日：2010-11-10

申请人： Si-Hwan Kim ,  Joon-Suc Jang ,  Ki-Hwan Choi ,  Duck-Kyun Woo

发明人： Si-Hwan Kim ,  Joon-Suc Jang ,  Ki-Hwan Choi ,  Duck-Kyun Woo

IPC分类号： H03M13/00

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2029/0411

摘要： A flash memory device includes a plurality of memory cells each configured to store k-bit data, where k is a natural number greater than one. The device is programmed by a method including reading (i−1)-th order data from a selected memory cell connected to a selected wordline before programming i-th order data in one or more adjacent memory cells connected to an adjacent wordline, wherein i is a natural number between two and k, storing as read data the (i−1)-th order data read from the selected memory cell, and programming i-th order data in the selected memory cell based on the stored read data.

摘要翻译： 闪存器件包括多个存储器单元，每个存储器单元被配置为存储k位数据，其中k是大于1的自然数。 该装置通过一种方法来编程，包括在连接到相邻字线的一个或多个相邻存储器单元中编程i阶数据之前从连接到选定字线的选定存储单元读取（i-1）数据，其中i 是两个和k之间的自然数，作为读取数据存储从所选择的存储单元读取的（i-1）数据数据，以及基于所存储的读取数据在所选择的存储器单元中编程i阶数据。

公开(公告)号：US20110122697A1

公开(公告)日：2011-05-26

申请号：US12910063

申请日：2010-10-22

申请人： Joon-Suc Jang ,  Ki-Hwan Choi ,  Duck-Kyun Woo ,  Si-Hwan Kim

发明人： Joon-Suc Jang ,  Ki-Hwan Choi ,  Duck-Kyun Woo ,  Si-Hwan Kim

IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C16/3418

摘要： A method of programming a nonvolatile memory device is disclosed. The method includes providing a plurality of memory cells coupled to a wordline, the plurality of memory cells grouped into a plurality of groups, each group including at least two memory cells, such that for each cell of the plurality of memory cells that has memory cells adjacent both sides, the memory cells immediately adjacent either side of the cell belong to different groups from each other. The method further includes selecting one group from the plurality of groups, and performing a program operation including applying a program pulse to the selected group while one or more non-selected groups of the plurality of groups are inhibited from being programmed.

摘要翻译： 公开了一种非易失性存储器件的编程方法。 所述方法包括提供耦合到字线的多个存储器单元，所述多个存储器单元分组成多个组，每个组包括至少两个存储器单元，使得对于具有存储器单元的多个存储器单元中的每个单元 相邻两侧，紧邻细胞两侧的存储单元彼此不同。 该方法还包括从多个组中选择一个组，并且执行编程操作，包括在禁止编程多个组中的一个或多个未选择的组时将编程脉冲施加到所选择的组。

公开(公告)号：US06442071B1

公开(公告)日：2002-08-27

申请号：US09731537

申请日：2000-12-06

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C1606

摘要： A flash memory device with an improved erase algorithm for erasing a plurality of memory cells that are arranged in intersections of wordlines and bitlines, respectively, includes an array of the memory cells. In the erase algorithm, all memory cells of the sector are erased at the same time. A pass/fail check & control logic then checks whether the memory cells are overerased. When one of a group of the erased memory cells is overerased, soft-program voltages are applied to the overerased memory cells such that the over-erased memory cells become soft-programmed. After boosting one of the soft-program voltages, the operations of checking, soft-programming, and boosting are carried out repeatedly, until a threshold voltage of the overerased memory cell moves within a target threshold voltage range of the erased memory cell. Therefore, overerasing is cured based upon program characteristics, without overcuring.

公开(公告)号：US6151250A

公开(公告)日：2000-11-21

申请号：US430444

申请日：1999-10-29

申请人： Ki-Hwan Choi ,  Jong-Min Park

发明人： Ki-Hwan Choi ,  Jong-Min Park

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  G11C16/34 ,  G11C17/00

CPC分类号： G11C16/3445 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3436 ,  G11C16/3459

摘要： A word line voltage supply circuit for a nonvolatile semiconductor memory device reduces power supply noise by deactivating a high voltage generator during a verify sensing operation. The word line voltage supply circuit includes a high voltage generator that produces a high voltage signal in response to a control signal from a controller. A voltage regulator regulates the high voltage signal to generate a verify voltage signal that is applied to a selected memory cell. The controller deactivates the control signal during a verify sensing operation so as to eliminate power supply noise caused by the pumping operation of the high voltage generator.

摘要翻译： 用于非易失性半导体存储器件的字线电压供应电路在验证感测操作期间通过去激活高电压发生器来降低电源噪声。 字线电压供应电路包括响应于来自控制器的控制信号产生高电压信号的高压发生器。 电压调节器调节高电压信号以产生施加到所选存储器单元的验证电压信号。 在验证感测操作期间，控制器禁用控制信号，以消除由高压发生器的泵送操作引起的电源噪声。

公开(公告)号：US5986947A

公开(公告)日：1999-11-16

申请号：US57784

申请日：1998-04-09

申请人： Ki-Hwan Choi ,  Seung-Keun Lee ,  Kang-Deog Suh

发明人： Ki-Hwan Choi ,  Seung-Keun Lee ,  Kang-Deog Suh

IPC分类号： G11C16/06 ,  G11C5/14 ,  G11C16/12 ,  H02M3/07 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C5/145 ,  H02M3/073

摘要： The well regions of pumping units of charge pump circuits are maintained electrically floating. By maintaining the wells electrically floating, reduced impact from the body effect may be obtained. More specifically, integrated circuit charge pump circuits boost a first voltage from a voltage source to a second voltage at an output terminal. The charge pump circuits include a plurality of pumping units in an integrated circuit substrate of first conductivity type, that are serially connected between the voltage source and the output terminal. Each of the pumping units includes a well region of second conductivity type in the integrated circuit substrate of first conductivity type. The well region of second conductivity type is electrically floating. Each pumping unit also includes a transistor of the first conductivity type in the floating well region of second conductivity type, and a capacitor that is electrically connected to the transistor of the first conductivity type in the floating well region of second conductivity type.

摘要翻译： 电荷泵电路的泵浦单元的阱区保持电浮动。 通过维持井电浮动，可以获得来自身体效应的减小的冲击。 更具体地，集成电路电荷泵电路在输出端将电压源的第一电压提升到第二电压。 电荷泵电路包括在第一导电类型的集成电路衬底中的多个泵送单元，其串联连接在电压源和输出端子之间。 每个泵送单元在第一导电类型的集成电路基板中包括第二导电类型的阱区域。 第二导电类型的阱区域是电浮动的。 每个泵送单元还包括在第二导电类型的浮动阱区域中的第一导电类型的晶体管，以及在第二导电类型的浮动阱区域中电连接到第一导电类型的晶体管的电容器。