公开(公告)号：US07539063B2

公开(公告)日：2009-05-26

申请号：US11651521

申请日：2007-01-10

申请人： Sang-Gu Kang ,  Young-Ho Lim

发明人： Sang-Gu Kang ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C11/5628

摘要： Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells into a provisional state according to the least significant bit, and programming the plurality of memory cells into the second through fourth states from the first and provisional states according to the most significant bit. Programming the plurality of memory cells into the second through fourth states includes simultaneously programming the plurality of memory cells at least partially into at least two states during one programming operation period.

摘要翻译： 提供闪存设备及其编程方法。 闪速存储器件包括存储多位数据的多个存储单元，该多位数据表示第一至第四状态中的至少一个，并且包括最高有效位和最低有效位。 该方法包括根据最低有效位将多个存储器单元编程为临时状态，并根据最高有效位将第一至暂态状态的多个存储单元编程为第二至第四状态。 将多个存储器单元编程为第二至第四状态包括在一个编程操作周期期间至少部分地将多个存储器单元编程为至少两个状态。

公开(公告)号：US07489558B2

公开(公告)日：2009-02-10

申请号：US11700834

申请日：2007-02-01

申请人： Ki-Hwan Choi ,  Young-Ho Lim

发明人： Ki-Hwan Choi ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method.

摘要翻译： 本发明提供了一种闪速存储装置的编程方法，其包括用于存储指示多个状态之一的多位数据的多个存储单元。 对存储器单元进行主程序操作。 布置在各个状态的特定区域内的那些存储单元经受二次编程操作，以具有等于或高于在主程序操作中使用的验证电压的阈值电压。 因此，尽管由于电场耦合/ F-poly耦合和HTS而使阈值电压分布变宽，但是可以使用编程方法充分确保相邻状态之间的读取余量。

公开(公告)号：US20090016111A1

公开(公告)日：2009-01-15

申请号：US12216593

申请日：2008-07-08

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/3427

摘要： A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

摘要翻译： 一种对闪存进行编程的方法包括通过向所选择的字线施加第一电压并将第二电压施加到未选择的字线来连接到所选字线的编程存储单元，所述第二电压低于所述第一电压， 在对连接到所选字线的存储单元进行编程之后，所选字线的第一电压为第三电压，第三电压低于第一电压，并且恢复所选字线和未选字线的第四电压 ，第四电压低于第二和第三电压。

公开(公告)号：US20080316834A1

公开(公告)日：2008-12-25

申请号：US12201977

申请日：2008-08-29

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C16/349

摘要： A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

摘要翻译： 非易失性半导体存储器件包括：连接到相应位线的单元串; 每个单元串具有连接到串选择线的串选择晶体管，连接到接地选择线的接地选择晶体管和连接到对应字线并且串联连接在串选择晶体管和接地选择晶体管之间的存储单元 ; 第一电压降电路，被配置为在读取操作期间减小施加的读取电压; 配置为减小所施加的读取电压的第二电压降电路; 串行选择线驱动电路，被配置为利用由第一压降电路提供的降低的电压驱动串选择线; 以及接地选择线驱动电路，被配置为用由第二压降电路提供的降低的电压来驱动接地选择线。

公开(公告)号：US07457168B2

公开(公告)日：2008-11-25

申请号：US11871297

申请日：2007-10-12

申请人： Jae-Yong Jeong ,  Young-Ho Lim

发明人： Jae-Yong Jeong ,  Young-Ho Lim

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C8/00

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

摘要翻译： 公开了一种非易失性存储器件和擦除非易失性存储器件的方法。 同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。 然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。 根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。 在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

公开(公告)号：US20060120172A1

公开(公告)日：2006-06-08

申请号：US11228189

申请日：2005-09-19

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C7/10

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

摘要翻译： 在一个方面，提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US06654290B2

公开(公告)日：2003-11-25

申请号：US09995500

申请日：2001-11-26

申请人： Seung-Keun Lee ,  Young-Ho Lim

发明人： Seung-Keun Lee ,  Young-Ho Lim

IPC分类号： G11C1606

CPC分类号： G11C29/12005 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

摘要： A flash memory device includes a column selector, a voltage switch circuit, and a plurality of write drivers. The column selector selects one of bitlines of each group, and the voltage switch circuit selects a program voltage from a high voltage pump circuit or an external voltage from an external voltage pad. The write drivers are connected to input/output pads through corresponding data input buffers. For a test operation mode to measure a cell current, each of the write drivers transfers or cuts off a voltage, selected by the voltage switch circuit, to a selected bitline of a corresponding group in response to a data bit signal applied to a corresponding input/output pad. Thus, the write drivers are used to measure a cell current of a memory cell without extra path gates.

公开(公告)号：US06545920B2

公开(公告)日：2003-04-08

申请号：US09967102

申请日：2001-09-28

申请人： Byeong-Hoon Lee ,  Young-Ho Lim

发明人： Byeong-Hoon Lee ,  Young-Ho Lim

IPC分类号： G11C700

CPC分类号： G11C29/785

摘要： A defective address storage circuit reduces current consumption in a memory device by utilizing a fuse block having address storage blocks arranged in series. Each address storage block preferably has two portions, each portion having a fuse and transistor. A NAND-type architecture can be implemented by arranging the portions of each block in parallel while the fuse and transistor are arranged in series, or by arranging the portions of each block in series while the fuse and transistor are arranged in parallel.

公开(公告)号：US08493785B2

公开(公告)日：2013-07-23

申请号：US13465246

申请日：2012-05-07

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离的锁存器输出路径。

公开(公告)号：US07768831B2

公开(公告)日：2010-08-03

申请号：US12109466

申请日：2008-04-25

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

摘要翻译： 闪存器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，以及被配置为响应于块地址产生块选择信号的控制器。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。