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    Decomposition based approach for the synthesis of threshold logic circuits
    11.
    发明授权
    Decomposition based approach for the synthesis of threshold logic circuits 有权
    用于合成阈值逻辑电路的基于分解的方法

    公开(公告)号：US08601417B2

    公开(公告)日：2013-12-03

    申请号：US13090796

    申请日：2011-04-20

    申请人： Tejaswi Gowda ,  Sarma Vrudhula

    发明人： Tejaswi Gowda ,  Sarma Vrudhula

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process.

    摘要翻译： 公开了用于将布尔函数识别为阈值函数或非阈值函数的系统和方法。 在一个实施例中，为了将布尔函数识别为阈值函数或非阈值函数，首先确定布尔函数是否满足作为阈值函数的一个或多个预定义条件，其中，一个或 更多的预定义条件包括布尔函数的正辅助因子和负辅助因子都是阈值函数的条件。 如果满足一个或多个预定条件，则确定正和负辅助因子的权重是否相等。 如果辅因子的权重相等，则布尔函数被确定为阈值函数。 此外，在一个实施例中，该阈值函数识别处理被用于阈值电路合成处理。

    FPGA with reconfigurable threshold logic gates for improved performance, power, and area
    12.
    发明授权
    FPGA with reconfigurable threshold logic gates for improved performance, power, and area 有权

    公开(公告)号：US11356100B2

    公开(公告)日：2022-06-07

    申请号：US16926718

    申请日：2020-07-12

    申请人： Sarma Vrudhula ,  Ankit Wagle

    发明人： Sarma Vrudhula ,  Ankit Wagle

    IPC分类号： H03K19/17728 ,  G06F30/343 ,  H03K19/17796 ,  H03K19/17736 ,  G06F30/347 ,  G06F119/06

    摘要： A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.

    FPGA WITH RECONFIGURABLE THRESHOLD LOGIC GATES FOR IMPROVED PERFORMANCE, POWER, AND AREA
    13.
    发明申请
    FPGA WITH RECONFIGURABLE THRESHOLD LOGIC GATES FOR IMPROVED PERFORMANCE, POWER, AND AREA 有权

    公开(公告)号：US20210013886A1

    公开(公告)日：2021-01-14

    申请号：US16926718

    申请日：2020-07-12

    申请人： Sarma Vrudhula ,  Ankit Wagle

    发明人： Sarma Vrudhula ,  Ankit Wagle

    IPC分类号： H03K19/17728 ,  G06F30/343 ,  G06F30/347 ,  H03K19/17796 ,  H03K19/17736

    摘要： A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.

    THRESHOLD GATE AND THRESHOLD LOGIC ARRAY
    16.
    发明申请
    THRESHOLD GATE AND THRESHOLD LOGIC ARRAY 有权
    阈值门和阈值逻辑阵列

    公开(公告)号：US20130313623A1

    公开(公告)日：2013-11-28

    申请号：US13903490

    申请日：2013-05-28

    申请人： Sarma Vrudhula ,  Nishant S. Nukala ,  Niranjan Kulkarni

    发明人： Sarma Vrudhula ,  Nishant S. Nukala ,  Niranjan Kulkarni

    IPC分类号： H01L43/02

    CPC分类号： H01L43/02 ,  H03K19/18 ,  H03K19/20 ,  H03K19/23

    摘要： Threshold gates and related circuitry are disclosed. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the threshold realization element is configured to switch the magnetic tunnel junction element from the first resistive state to the second resistive state in accordance with the threshold function. In this manner, the threshold gate may implement a threshold function that provides an output just like a complex Boolean function requiring several Boolean gates.

    摘要翻译： 公开了阈值门和相关电路。 在一个实施例中，阈值门包括阈值实现元件和磁性隧道结（MTJ）元件。 MTJ元件可从第一电阻状态切换到第二电阻状态。 为了实现具有MTJ元件的阈值函数，阈值实现元件被配置为根据阈值函数将磁隧道结元件从第一电阻状态切换到第二电阻状态。 以这种方式，阈值门可以实现提供输出的阈值函数，就像需要几个布尔门的复数布尔函数。

    Method of evaluating integrated circuit system performance using orthogonal polynomials
    17.
    发明授权
    Method of evaluating integrated circuit system performance using orthogonal polynomials 失效
    使用正交多项式评估集成电路系统性能的方法

    公开(公告)号：US07630852B1

    公开(公告)日：2009-12-08

    申请号：US11556766

    申请日：2006-11-06

    申请人： Praveen Ghanta ,  Sarma Vrudhula ,  Sarvesh Bhardwaj

    发明人： Praveen Ghanta ,  Sarma Vrudhula ,  Sarvesh Bhardwaj

    IPC分类号： G01R27/28

    CPC分类号： G06F17/5036

    摘要： A method for analyzing IC system performance. The method includes receiving system variables that correspond to an IC system; normalizing the system variables; using an infinite dimensional Hilbert space, modeling a system response as a series of series of orthogonal polynomials; and, solving for coefficients of the series of orthogonal polynomials. A system equation or a simulated response may be used to solve for the coefficients. If a simulated response is used, the coefficients may be solved by using the statistical expectance of the product of the simulated system response and the series of orthogonal polynomials. Alternatively, a simulated system response may be used to generate coefficients by performing a least mean square fit.

    摘要翻译： 一种分析IC系统性能的方法。 该方法包括接收对应于IC系统的系统变量; 规范化系统变量; 使用无限维希尔伯特空间，将系统响应建模为一系列正交多项式; 并求解该系列正交多项式的系数。 可以使用系统方程或模拟响应来求解系数。 如果使用模拟响应，可以通过使用仿真系统响应和一系列正交多项式的乘积的统计期望来解决系数。 或者，可以使用模拟系统响应来通过执行最小均方拟合来生成系数。

    Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
    18.
    发明授权
    Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs 有权

    公开(公告)号：US10551869B2

    公开(公告)日：2020-02-04

    申请号：US15443444

    申请日：2017-02-27

    申请人： Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni

    发明人： Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni

    IPC分类号： G06F1/12 ,  G06F1/10

    摘要： This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

    Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits
    19.
    发明授权
    Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits 有权

    公开(公告)号：US10447249B2

    公开(公告)日：2019-10-15

    申请号：US15568858

    申请日：2016-05-23

    申请人： Sarma Vrudhula ,  Niranjan Kulkarni

    发明人： Sarma Vrudhula ,  Niranjan Kulkarni

    IPC分类号： H03K3/356 ,  G01R31/3185 ,  H03K3/037 ,  G01R31/3177

    摘要： A sequential state element (SSE) is disclosed. In one embodiment, an SSE includes a differential sense flip flop (DSFF) and a completion detection circuit (CDC) operably associated with the DSFF. The DSFF is configured to generate a differential logical output. During a normal operational mode, the DSFF is synchronized by a clock signal to provide a differential logical output in a differential output state in accordance with a data input or in a precharge state based on the clock signal. The differential logical output is provided in a differential output state in accordance with a test input during a scan mode. The CDC is configured to generate a test enable input during the scan mode that indicates the scan mode once the differential logical output is in the differential output state. Accordingly, another SSE can be asynchronously triggered to operate in the scan mode without a separate scan clock.

    Threshold logic element with stabilizing feedback
    20.
    发明授权
    Threshold logic element with stabilizing feedback 有权
    具有稳定反馈的阈值逻辑元件

    公开(公告)号：US09473139B2

    公开(公告)日：2016-10-18

    申请号：US14792183

    申请日：2015-07-06

    申请人： Sarma Vrudhula ,  Niranjan Kulkarni

    发明人： Sarma Vrudhula ,  Niranjan Kulkarni

    IPC分类号： H03K19/094 ,  G11C7/00 ,  H03K19/003 ,  G11C7/06 ,  G11C11/16 ,  G11C13/00 ,  H03K19/00 ,  H03K19/017 ,  H03K19/096 ,  H03K19/21

    CPC分类号： H03K19/00361 ,  G11C7/065 ,  G11C11/1673 ,  G11C13/004 ,  H03K19/0027 ,  H03K19/01707 ,  H03K19/0963 ,  H03K19/215

    摘要： Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise.

    摘要翻译： 公开了阈值逻辑元件及其操作方法。 在一个实施例中，阈值逻辑元件包括被配置为接收第一组逻辑信号的第一输入门网络，被配置为接收第二组逻辑信号的第二输入门网络。 差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分逻辑输出。 为了使阈值逻辑元件更稳健，差分读出放大器被配置为将差分逻辑输出反馈到第一输入门网络和第二输入门网络。 通过提供差分逻辑输出作为反馈，避免了浮动节点问题，并且阈值逻辑元件更能抵抗噪声。