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    Semiconductor integrated circuit device and a manufacturing method thereof
    11.
    发明授权
    Semiconductor integrated circuit device and a manufacturing method thereof 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US5604365A

    公开(公告)日：1997-02-18

    申请号：US297039

    申请日：1994-08-29

    申请人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana

    发明人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/105 ,  H01L27/10805

    摘要： A semiconductor integrated circuit device having a DRAM consisting of memory cells, comprises; a first conductive film deposited over the main surface of a semiconductor substrate and used to form a gate electrode of a memory cell selection MISFET; a second conductive film deposited over the first conductive film and used to form bit lines to transfer data of a memory cell to a sense amplifier; a third conductive film deposited over the second conductive film and used to form a storage node of a capacitor; a fourth conductive film deposited over the third conductive film and used to form a plate electrode of the capacitor; and a fifth conductive film deposited over the fourth conductive film and used to form an interconnect, wherein a transistor in a direct peripheral circuit arranged close to a memory array is electrically connected, through a pad layer formed of the third conductive film, to the interconnection of the fifth conductive film deposited over the fourth conductive film, thereby allowing the aspect ratio of the contact hole formed over the pad layer to be reduced.

    摘要翻译： 一种具有由存储单元组成的DRAM的半导体集成电路器件，包括： 沉积在半导体衬底的主表面上并用于形成存储器单元选择MISFET的栅电极的第一导电膜; 沉积在第一导电膜上并用于形成位线以将存储器单元的数据传送到读出放大器的第二导电膜; 沉积在所述第二导电膜上并用于形成电容器的存储节点的第三导电膜; 沉积在所述第三导电膜上并用于形成所述电容器的平板电极的第四导电膜; 以及沉积在第四导电膜上并用于形成互连的第五导电膜，其中布置在存储器阵列附近的直接外围电路中的晶体管通过由第三导电膜形成的焊盘层电连接到互连 所述第五导电膜沉积在所述第四导电膜上，从而允许形成在所述焊盘层上的所述接触孔的纵横比减小。

    Method of manufacturing a semiconductor integrated circuit device having a capacitor
    14.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device having a capacitor 失效
    具有电容器的半导体集成电路器件的制造方法

    公开(公告)号：US5976929A

    公开(公告)日：1999-11-02

    申请号：US962878

    申请日：1997-11-03

    申请人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana ,  Goro Kitsukawa

    发明人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana ,  Goro Kitsukawa

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/105 ,  H01L27/10805

    摘要： A semiconductor integrated circuit device having a DRAM consisting of memory cells, comprises; a first conductive film deposited over the main surface of a semiconductor substrate and used to form a gate electrode of a memory cell selection MISFET; a second conductive film deposited over the first conductive film and used to form bit lines to transfer data of a memory cell to a sense amplifier; a third conductive film deposited over the second conductive film and used to form a storage node of a capacitor; a fourth conductive film deposited over the third conductive film and used to form a plate electrode of the capacitor; and a fifth conductive film deposited over the fourth conductive film and used to form an interconnect, wherein a transistor in a direct peripheral circuit arranged close to a memory array is electrically connected, through a pad layer formed of the third conductive film, to the interconnection of the fifth conductive film deposited over the fourth conductive film, thereby allowing the aspect ratio of the contact hole formed over the pad layer to be reduced.

    摘要翻译： 一种具有由存储单元组成的DRAM的半导体集成电路器件，包括： 沉积在半导体衬底的主表面上并用于形成存储器单元选择MISFET的栅电极的第一导电膜; 沉积在第一导电膜上并用于形成位线以将存储器单元的数据传送到读出放大器的第二导电膜; 沉积在所述第二导电膜上并用于形成电容器的存储节点的第三导电膜; 沉积在所述第三导电膜上并用于形成所述电容器的平板电极的第四导电膜; 以及沉积在第四导电膜上并用于形成互连的第五导电膜，其中布置在存储器阵列附近的直接外围电路中的晶体管通过由第三导电膜形成的焊盘层电连接到互连 所述第五导电膜沉积在所述第四导电膜上，从而允许形成在所述焊盘层上的所述接触孔的纵横比减小。