公开(公告)号：US20120061682A1

公开(公告)日：2012-03-15

申请号：US13229892

申请日：2011-09-12

申请人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.

摘要翻译： SiC半导体器件包括：依次堆叠的衬底，漂移层和基极区域; 第一和第二源极区域和基极区域中的接触层; 穿透源区和基区的沟槽; 沟槽中的栅电极; 具有覆盖所述栅电极的接触孔的层间绝缘膜; 源极通过接触孔与源极区域和接触层耦合; 衬底上的漏电极; 和金属硅化物膜。 高浓度第二源区比低浓度第一源区浅，并且具有被层间绝缘膜覆盖的部分，其包括表面附近的低浓度第一部分和比第一部分更深的高浓度第二部分。 第二部分上的金属硅化物膜的厚度大于第一部分。

公开(公告)号：US20110203513A1

公开(公告)日：2011-08-25

申请号：US13029791

申请日：2011-02-17

申请人： Hiroki WATANABE ,  Yasuo Kitou ,  Kensaku Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Hiroki WATANABE ,  Yasuo Kitou ,  Kensaku Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： C30B19/12

CPC分类号： H01L21/02529 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02378 ,  H01L21/02658 ,  H01L21/02667 ,  H01L29/66068

摘要： In a method of manufacturing a silicon carbide substrate, a defect-containing substrate made of silicon carbide is prepared. The defect-containing substrate has a front surface, a rear surface being opposite to the front surface, and a surface portion adjacent to the front surface. The detect-containing substrate includes a screw dislocation in the surface portion. The front surface of the defect-containing substrate is applied with an external force so that a crystallinity of the surface portion is reduced. After being applied with the external force, the defect-containing substrate is thermally treated so that the crystallinity of the surface portion is recovered.

摘要翻译： 在制造碳化硅衬底的方法中，制备由碳化硅制成的含缺陷衬底。 含缺陷的基板具有前表面，与前表面相对的后表面和与前表面相邻的表面部分。 含检测基板包括在表面部分中的螺旋位错。 使含有缺陷的基板的前表面被施加外力，使得表面部分的结晶度降低。 在施加外力之后，对含缺陷的基板进行热处理，以恢复表面部分的结晶度。

公开(公告)号：US20140175459A1

公开(公告)日：2014-06-26

申请号：US13994855

申请日：2012-02-06

申请人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.

摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层具有上部和下部。 上部的宽度小于下部。

公开(公告)号：US20110309464A1

公开(公告)日：2011-12-22

申请号：US13164246

申请日：2011-06-20

申请人： Kensaku YAMAMOTO ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku YAMAMOTO ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8613

摘要： A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

摘要翻译： 半导体器件包括半导体衬底和电场端子部分。 半导体衬底包括衬底，设置在衬底的表面上的漂移层和设置在漂移层的表面上的基底层。 半导体衬底被分成其中设置半导体元件的单元区域和围绕单元区域的外围区域。 基底区域具有位于整个电池区域和外围区域的同一平面上的底面，并且提供位于周边区域中的电场弛豫层。 电场端子部围绕电池区域和电场缓和层的一部分，从电场缓和层的表面向漂移层贯通电场缓和层。

公开(公告)号：US08618555B2

公开(公告)日：2013-12-31

申请号：US13117575

申请日：2011-05-27

申请人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。 深层设置在基底区域下方并且位于比沟槽更深的深度。 深层在与沟槽的纵向方向交叉的方向上分成多个部分。 这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。 该组部分围绕沟槽的底部的角落。

公开(公告)号：US08492867B2

公开(公告)日：2013-07-23

申请号：US13164246

申请日：2011-06-20

申请人： Kensaku Yamamoto ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8613

摘要： A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

摘要翻译： 半导体器件包括半导体衬底和电场端子部分。 半导体衬底包括衬底，设置在衬底的表面上的漂移层和设置在漂移层的表面上的基底层。 半导体衬底被分成其中设置半导体元件的单元区域和围绕单元区域的外围区域。 基底区域具有位于整个电池区域和外围区域的同一平面上的底面，并且提供位于周边区域中的电场弛豫层。 电场端子部围绕电池区域和电场缓和层的一部分，从电场缓和层的表面向漂移层贯通电场缓和层。

公开(公告)号：US08334541B2

公开(公告)日：2012-12-18

申请号：US13177747

申请日：2011-07-07

申请人： Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

发明人： Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7828

摘要： A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.

摘要翻译： SiC半导体器件包括：反向型MOSFET，具有：衬底; 衬底上的漂移层和基极区域; 基极接触层和基极区上的源极区; 多个沟槽具有沿着第一方向的纵向方向穿过源极区域和基极区域; 通过栅极绝缘膜在每个沟槽中的栅电极; 覆盖所述栅电极且具有接触孔的层间绝缘膜，所述源极区域和所述基极接触层暴露在所述接触孔中; 源极通过接触孔与源极区域和基极区域耦合; 衬底上的漏电极。 源区域和基底接触层与垂直于第一方向的第二方向一起延伸，并且与第一方向交替布置。 接触孔沿第一方向具有纵向方向。

公开(公告)号：US20120012860A1

公开(公告)日：2012-01-19

申请号：US13177747

申请日：2011-07-07

申请人： Shinichiro MIYAHARA ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

发明人： Shinichiro MIYAHARA ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7828

摘要： A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.

摘要翻译： SiC半导体器件包括：反向型MOSFET，具有：衬底; 衬底上的漂移层和基极区域; 基极接触层和基极区上的源极区; 多个沟槽具有沿着第一方向的纵向方向穿过源极区域和基极区域; 通过栅极绝缘膜在每个沟槽中的栅电极; 覆盖所述栅电极且具有接触孔的层间绝缘膜，所述源极区域和所述基极接触层暴露在所述接触孔中; 源极通过接触孔与源极区域和基极区域耦合; 衬底上的漏电极。 源区域和基底接触层与垂直于第一方向的第二方向一起延伸，并且与第一方向交替布置。 接触孔沿第一方向具有纵向方向。

公开(公告)号：US09024330B2

公开(公告)日：2015-05-05

申请号：US14141174

申请日：2013-12-26

申请人： Yukihiko Watanabe ,  Sachiko Aoi ,  Masahiro Sugimoto ,  Akitaka Soeno ,  Shinichiro Miyahara

发明人： Yukihiko Watanabe ,  Sachiko Aoi ,  Masahiro Sugimoto ,  Akitaka Soeno ,  Shinichiro Miyahara

IPC分类号： H01L29/47 ,  H01L29/45 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0485 ,  H01L21/28518 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

摘要翻译： 一种制造半导体器件的方法包括：在碳化硅层的一个主表面上的第一区域中形成欧姆电极，将欧姆电极硅化，并在第二区域中形成肖特基电极 具有自对准的碳化硅层。 在没有形成欧姆电极的情况下暴露第二区域。

公开(公告)号：US07777252B2

公开(公告)日：2010-08-17

申请号：US11632665

申请日：2005-06-22

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/739 ,  H01L31/072

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。