公开(公告)号：US20120319136A1

公开(公告)日：2012-12-20

申请号：US13581497

申请日：2012-02-06

申请人： Masato Noborio ,  Kensaku Yamamoto ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Masato Noborio ,  Kensaku Yamamoto ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC device includes an inversion type MOSFET having: a substrate, a drift layer, and a base region stacked in this order; source and contact regions in upper portions of the base region; a trench penetrating the source and base regions; a gate electrode on a gate insulating film in the trench; a source electrode coupled with the source and base region; a drain electrode on a back of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has an impurity concentration distribution in a depth direction, and an inversion layer is provided in a portion of the deep layer on the side of the trench under application of the gate voltage.

摘要翻译： SiC器件包括反转型MOSFET，其具有：依次堆叠的衬底，漂移层和基极区域; 源极和接触区域在基极区域的上部; 穿透源区和基区的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极与源极和基极区域耦合; 位于衬底背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层在深度方向上具有杂质浓度分布，并且在施加栅极电压下在沟槽侧的深层的一部分中设置反转层。

公开(公告)号：US20140175459A1

公开(公告)日：2014-06-26

申请号：US13994855

申请日：2012-02-06

申请人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.

摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层具有上部和下部。 上部的宽度小于下部。

公开(公告)号：US08618555B2

公开(公告)日：2013-12-31

申请号：US13117575

申请日：2011-05-27

申请人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。 深层设置在基底区域下方并且位于比沟槽更深的深度。 深层在与沟槽的纵向方向交叉的方向上分成多个部分。 这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。 该组部分围绕沟槽的底部的角落。

公开(公告)号：US20140252465A1

公开(公告)日：2014-09-11

申请号：US14352142

申请日：2012-10-17

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L21/047 ,  H01L21/28008 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于 半导体衬底的表面，源区域通过身体区域与漂移区隔离。 特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。 绝缘层覆盖特定层的上表面和沟槽的侧壁。 导电部分形成在沟槽的侧壁的一部分上。 导电部分连接到特定层，并到达半导体衬底的表面。

公开(公告)号：US09276075B2

公开(公告)日：2016-03-01

申请号：US14352142

申请日：2012-10-17

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L21/04 ,  H01L29/16

CPC分类号： H01L29/4236 ,  H01L21/047 ,  H01L21/28008 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于 半导体衬底的表面，源区域通过身体区域与漂移区隔离。 特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。 绝缘层覆盖特定层的上表面和沟槽的侧壁。 导电部分形成在沟槽的侧壁的一部分上。 导电部分连接到特定层，并到达半导体衬底的表面。

公开(公告)号：US08952430B2

公开(公告)日：2015-02-10

申请号：US13703284

申请日：2011-06-02

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/76 ,  H01L29/16 ,  H01L29/49 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/49 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.

摘要翻译： 本申请涉及用于提高半导体器件耐受电压的技术。 半导体器件包括围绕单元区域的终止区域。 单元区域设置有多个主沟槽。 终端区域设置有围绕单元区域的一个或多个终止沟槽。 终端沟槽设置在一个或多个端接沟槽的最内圆周处。 体区域设置在漂移区域的表面上。 每个主沟槽到达漂移区域。 在每个主沟槽内设置栅电极。 端接沟槽到达漂移区域。 侧壁和终端沟槽的底表面被绝缘层覆盖。 覆盖终端沟槽的底面的绝缘层的表面被掩埋电极覆盖。 将栅极电位施加到掩埋电极。

公开(公告)号：US20130075760A1

公开(公告)日：2013-03-28

申请号：US13703284

申请日：2011-06-02

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/16 ,  H01L29/49

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/49 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.

摘要翻译： 本申请涉及用于提高半导体器件耐受电压的技术。 半导体器件包括围绕单元区域的终止区域。 单元区域设置有多个主沟槽。 终端区域设置有围绕单元区域的一个或多个终止沟槽。 终端沟槽设置在一个或多个端接沟槽的最内圆周处。 体区域设置在漂移区域的表面上。 每个主沟槽到达漂移区域。 在每个主沟槽内设置栅电极。 端接沟槽到达漂移区域。 侧壁和终端沟槽的底表面被绝缘层覆盖。 覆盖终端沟槽的底面的绝缘层的表面被掩埋电极覆盖。 将栅极电位施加到掩埋电极。

公开(公告)号：US07417309B2

公开(公告)日：2008-08-26

申请号：US11320248

申请日：2005-12-27

申请人： Kouji Takahashi ,  Hideo Matsuki ,  Masami Ito ,  Naoyuki Aoki

发明人： Kouji Takahashi ,  Hideo Matsuki ,  Masami Ito ,  Naoyuki Aoki

IPC分类号： H01L23/02

CPC分类号： H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2224/05599

摘要： To provide a circuit device freed from constrains of a mounting direction. The circuit device according to the present invention includes: a conductive pattern for forming a die pad, a first bonding pad, and a second bonding pad; and a semiconductor element (TR) attached to the conductive pattern. The circuit device further includes: a sealing resin for covering the semiconductor element (TR) and the conductive pattern with a rear surface of the conductive pattern being exposed; and a coating resin for covering the rear surface of the conductive pattern exposed from the sealing resin. The rear surface of the conductive pattern is exposed from openings of the coating resin, and the openings are arranged with rotational symmetry about a central point of the circuit device.

摘要翻译： 为了提供一个电路装置，不受安装方向的约束。 根据本发明的电路装置包括：用于形成管芯焊盘的导电图案，第一焊盘和第二焊盘; 以及附接到导电图案的半导体元件（TR）。 电路装置还包括：用于覆盖半导体元件（TR）的密封树脂和导电图案的背面露出的导电图案; 以及用于覆盖从密封树脂露出的导电图案的后表面的涂覆树脂。 导电图案的后表面从涂覆树脂的开口露出，并且开口围绕电路装置的中心点以旋转对称的方式布置。

公开(公告)号：US3952006A

公开(公告)日：1976-04-20

申请号：US386819

申请日：1973-08-08

申请人： Tetsuya Tahara ,  Hideo Matsuki ,  Kazuhiko Araki ,  Masami Shiroki

发明人： Tetsuya Tahara ,  Hideo Matsuki ,  Kazuhiko Araki ,  Masami Shiroki

IPC分类号： C07D495/04 ,  C07D495/14 ,  C07D417/04

CPC分类号： C07D495/04 ,  C07D495/14

摘要： Thiophene derivatives of the formula: ##SPC1##Wherein R.sup.1 is H or CH.sub.3 ; R.sup.2 is CH.sub.3 or C.sub.2 H.sub.5, or R.sup.1 and R.sup.2 combinedly represent --(CH.sub.2).sub.4 --; each of R.sup.3 and R.sup.4 is H, alkyl of from 1 to 4 carbon atoms or cyclohexyl, or R.sup.3 and R.sup.4 together with the adjacent nitrogen atom form 1-pyrrolidinyl, piperidino, 4-methyl-1-piperazinyl or morpholino; X is H, halogen or OCH.sub.3 ; A is -CH= or --C(CH.sub.3)=, and B is =N-- or =CH--; or A is --C(CH.sub.2 OH)= or --N=, and B is =N--, and pharmaceutically acceptable acid addition salts thereof possess excellent pharmacological properties such as sedative, anxiolytic and anticonvulsant effects and protective effects against hypoxia or anoxia.

摘要翻译： 下式的噻吩衍生物：

公开(公告)号：US07365363B2

公开(公告)日：2008-04-29

申请号：US11108906

申请日：2005-04-19

申请人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

发明人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

IPC分类号： H01L31/0312

CPC分类号： H01L29/66068 ,  H01L21/02024 ,  H01L29/045 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7828

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate having a principal surface and a backside surface; a drift layer disposed on the principal surface; a base region disposed on the drift layer; a source region disposed on the base region; a surface channel layer disposed on both of the drift layer and the base region for connecting between the source region and the drift layer; a gate insulation film disposed on the surface channel layer and including a high dielectric constant film; a gate electrode disposed on the gate insulation film; a source electrode disposed on the source region; and a backside electrode disposed on the backside surface.

摘要翻译： 碳化硅半导体器件包括：具有主表面和背面的半导体衬底; 设置在主表面上的漂移层; 设置在漂移层上的基极区域; 设置在所述基底区域上的源极区域; 设置在所述漂移层和所述基极区域两者上的表面沟道层，用于在所述源极区域和所述漂移层之间连接; 栅极绝缘膜，设置在所述表面沟道层上并且包括高介电常数膜; 设置在所述栅极绝缘膜上的栅电极; 源电极，其设置在所述源极区域上; 以及设置在所述背面上的背面电极。