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公开(公告)号：US20120126735A1
公开(公告)日：2012-05-24
申请号：US13384706
申请日：2010-09-03
申请人： Yasuo Ueda , Masashi Tokuda , Toshihiro Tsukagoshi
发明人： Yasuo Ueda , Masashi Tokuda , Toshihiro Tsukagoshi
CPC分类号： H02M1/38 , H03K5/1515 , H03K17/16
摘要： A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.
摘要翻译： 死时间发生电路包括恒流电路; 产生电容器充电电流的电流产生电路; 以及接收死区时间控制信号和比较器信号的控制电路。 控制电路基于死区时间控制信号和比较器信号产生死区时间产生信号，并且基于死区时间产生信号产生充电/放电信号。 电容器的充电或放电根据充电/放电信号由电容器充电电流控制。 将电容器的电压与阈值电压进行比较，以便当电容器的电压超过阈值电压时产生比较器信号。 控制电路在从死区时间控制信号的上升或下降定时经过延迟时间直到控制电路接收到比较器信号为止的时间开始产生充电/放电信号。
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公开(公告)号：US08004323B2
公开(公告)日：2011-08-23
申请号：US12092227
申请日：2006-11-01
IPC分类号： H03L7/06
摘要： A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency.
摘要翻译： 响应于参考时钟输出PLL时钟的PLL控制电路设置有频率调节电路，其执行频率调整，使得即使在参考时钟变化时PLL时钟频率也基本恒定。 频率调整电路根据参考时钟频率的变化，在计数器中改变确定PLL时钟频率的设定值。
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公开(公告)号：US5828384A
公开(公告)日：1998-10-27
申请号：US711870
申请日：1996-09-12
CPC分类号： G09G5/395 , G09G5/399 , G09G2340/12 , G09G5/42
摘要： A VRAM stores a plurality of patterns of image data, an offset register stores values which indicate definition starting positions from which display image data are defined from the plurality of patterns of image data, respectively, a horizontal counter counts dots in a horizontal scanning direction, and a vertical counter counts lines in vertical scanning direction. Address and control signals are successively provided for reading a respective line of the display image data from the VRAM within one horizontal scanning period, based on the values of the offset register and the value of the vertical counter. Each of two second storage devices has a storage capacity for storing a thus-read respective line of the image data. Thus-read image data is written at addresses of a predetermined one of the two second storage devices, the addresses corresponding to displaying dots of the image data, while, according to the value of the horizontal counter, image data stored in the other one of the two second storage devices is read out, where, the image data writing and reading operations are performed alternately between the two second storage devices for each horizontal scanning period.
摘要翻译： VRAM存储多个图像数据图案，偏移寄存器分别存储指示从多个图像数据图案定义显示图像数据的定义开始位置的值，水平计数器对水平扫描方向计数点， 并且垂直计数器在垂直扫描方向上对行进行计数。 连续地提供地址和控制信号，用于基于偏移寄存器的值和垂直计数器的值，在一个水平扫描周期内从VRAM读取显示图像数据的相应行。 两个第二存储装置中的每一个具有用于存储如此读取的图像数据的相应行的存储容量。 这样读取的图像数据被写入两个第二存储装置中的预定的一个的地址，对应于显示图像数据的点的地址，而根据水平计数器的值，存储在另一个中的图像数据 读出两个第二存储装置，其中在每个水平扫描周期中，在两个第二存储装置之间交替地执行图像数据写入和读取操作。
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14.发明授权Neuron unit with error signal having components representing pulse densities 失效神经元单位，具有表示脉冲密度的分量的误差信号
公开(公告)号：US5504838A
公开(公告)日：1996-04-02
申请号：US206855
申请日：1994-03-07
申请人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Yutaka Ebi , Tatsuya Furukawa , Yoshio Watanabe , Toshihiro Tsukagoshi
发明人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Yutaka Ebi , Tatsuya Furukawa , Yoshio Watanabe , Toshihiro Tsukagoshi
CPC分类号： G06N3/063
摘要： A neuron unit processes a plurality of input signals and outputs an output signal which is indicative of a result of the processing. The neuron unit includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a generating part for generating new weight functions based on an error signal representing an error between the output signal of the forward process part and a teaching signal and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part. The error signal includes first and second error signal components representing pulse densities.
摘要翻译： 神经元单元处理多个输入信号并输出指示处理结果的输出信号。 神经元单元包括用于接收输入信号的输入线，包括用于提供加权函数的供给部分的前向处理部分和使用加权函数之一对每个输入信号执行操作的操作部分，并且用于输出输出 信号和自学习部分，包括用于基于表示正向处理部分的输出信号与示教信号之间的误差的误差信号产生新的加权函数的生成部分和用于改变由所述前向处理部分提供的加权函数的变化部分 将前向处理部分的一部分提供给由生成部分生成的新的加权函数。 误差信号包括表示脉冲密度的第一和第二误差信号分量。
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公开(公告)号：US5324991A
公开(公告)日：1994-06-28
申请号：US989605
申请日：1992-12-11
申请人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Atsuo Hashimoto , Sugitaka Oteki , Toshihiro Tsukagoshi , Satoshi Otsuki , Eiki Aono , Shuji Motomura , Takahiro Watanabe
发明人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Atsuo Hashimoto , Sugitaka Oteki , Toshihiro Tsukagoshi , Satoshi Otsuki , Eiki Aono , Shuji Motomura , Takahiro Watanabe
CPC分类号： G06N3/063
摘要： A neuron unit processes a plurality of binary input signals and outputs a neuron output signal which is indicative of a result of the processing. The neuron unit is provided with a plurality of first gates respectively for carrying out a logical operation on a binary input signal and a weighting coefficient, a second gate for carrying out a logical operation on an excitatory output signal of each of the first gates, a third gate for carrying out a logic operation on an inhibitory output signal of each of the first gates, a fourth gate for synthesizing output signals of the second and third gates and outputting the neuron output signal, and a generating circuit for generating the weighting coefficients which are supplied to each of the first gates. The generating circuit for generating one weighting coefficient includes a random number generator for generating random numbers, and a comparator for comparing each random number r with a predetermined value q and for outputting a pulse signal having first and second values depending on whether each random number r is such that r.ltoreq.q or r>q, and each weighting coefficient is described by a pulse density.
摘要翻译： 神经元单元处理多个二进制输入信号并输出指示处理结果的神经元输出信号。 神经元单元分别设置有多个第一门，用于对二进制输入信号和加权系数进行逻辑运算，第二门用于对每个第一门的兴奋性输出信号进行逻辑运算， 第三门，用于对每个第一门的抑制输出信号进行逻辑运算，第四门，用于合成第二和第三门的输出信号并输出神经元输出信号;以及产生电路，用于产生加权系数， 被提供给每个第一门。 用于产生一个加权系数的产生电路包括用于产生随机数的随机数发生器和用于将每个随机数r与预定值q进行比较的比较器，并且用于根据每个随机数r是否输出具有第一和第二值的脉冲信号 是这样的，r = q或r> q，并且每个加权系数由脉冲密度来描述。
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公开(公告)号：US4922441A
公开(公告)日：1990-05-01
申请号：US143715
申请日：1988-01-14
IPC分类号： G11C11/412 , G11C17/12 , H01L27/11 , H01L27/118 , H03K19/173 , G06F15/60
CPC分类号： H01L27/1104 , G11C11/412 , G11C17/12 , H01L27/11 , H01L27/1108 , H01L27/118 , H03K19/1735
摘要： A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.
摘要翻译： 门阵列器件包括彼此间隔开的多个基本单元区域，从而在其间限定多个中间区域。 每个中间区域可以至少部分地用作存储器或功能单元区域或者作为互连区域。 可以通过金属化将存储单元区域选择性地定义为ROM或RAM。 可以根据控制信号选择性地设置测试模式或正常操作模式。 当正常操作模式被设置时，输入端通过逻辑电路可操作地连接到存储器电路; 而当设置测试模式时，输入端直接连接到存储器电路，同时旁路逻辑电路。 还提供了一种存储单元结构，其可以被定义为RAM存储器单元或者通过金属化存储选择的二进制数据的ROM存储单元。
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公开(公告)号：US11312132B2
公开(公告)日：2022-04-26
申请号：US16999425
申请日：2020-08-21
摘要： There is provided a head driving device for causing a head to discharge droplets. The device includes a drive circuit, a first drive waveform generation circuit, a second drive waveform generation circuit, and a correction circuit. The drive circuit is configured to drive the head based on a plurality of drive waveforms to discharge the droplets. The first drive waveform generation circuit configured to generate a first drive waveform of the plurality of drive waveforms. The second drive waveform generation circuit is configured to generate a second drive waveform of the plurality of drive waveforms. The correction circuit is configured to correct the first drive waveform and the second drive waveform with reference to an intermediate potential.
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公开(公告)号：US08665003B2
公开(公告)日：2014-03-04
申请号：US13384706
申请日：2010-09-03
申请人： Yasuo Ueda , Masashi Tokuda , Toshihiro Tsukagoshi
发明人： Yasuo Ueda , Masashi Tokuda , Toshihiro Tsukagoshi
IPC分类号： H03K17/296
CPC分类号： H02M1/38 , H03K5/1515 , H03K17/16
摘要： A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.
摘要翻译： 死时间发生电路包括恒流电路; 产生电容器充电电流的电流产生电路; 以及接收死区时间控制信号和比较器信号的控制电路。 控制电路基于死区时间控制信号和比较器信号产生死区时间产生信号，并且基于死区时间产生信号产生充电/放电信号。 电容器的充电或放电根据充电/放电信号由电容器充电电流控制。 将电容器的电压与阈值电压进行比较，以便当电容器的电压超过阈值电压时产生比较器信号。 控制电路在从死区时间控制信号的上升或下降定时经过延迟时间直到控制电路接收到比较器信号为止的时间开始产生充电/放电信号。
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公开(公告)号：US20090267661A1
公开(公告)日：2009-10-29
申请号：US12092227
申请日：2006-11-01
IPC分类号： H03L7/06
摘要： A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency.
摘要翻译： 响应于参考时钟输出PLL时钟的PLL控制电路设置有频率调节电路，其执行频率调整，使得即使在参考时钟变化时PLL时钟频率也基本恒定。 频率调整电路根据参考时钟频率的变化，在计数器中改变确定PLL时钟频率的设定值。
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公开(公告)号：US5619617A
公开(公告)日：1997-04-08
申请号：US128707
申请日：1993-09-30
申请人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Yutaka Ebi , Tatsuya Furukawa , Yoshio Watanabe , Toshihiro Tsukagoshi
发明人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Yutaka Ebi , Tatsuya Furukawa , Yoshio Watanabe , Toshihiro Tsukagoshi
CPC分类号： G06N3/063
摘要： A neuron unit processes a plurality of input signals and outputs an output signal which is indicative of a result of the processing. The neuron unit includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a generating part for generating new weight functions based on errors between the output signal of the forward process part and teaching signals and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part.
摘要翻译： 神经元单元处理多个输入信号并输出指示处理结果的输出信号。 神经元单元包括用于接收输入信号的输入线，包括用于提供加权函数的供给部分的前向处理部分和使用加权函数之一对每个输入信号执行操作的操作部分，并且用于输出输出 信号和自学习部分，其包括基于正向处理部分的输出信号和示教信号之间的误差产生新的加权函数的生成部分和用于改变由前向处理的供给部分提供的加权函数的变化部分 部分由生成部分生成的新的权重函数。
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