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    System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory
    11.
    发明授权
    System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory 失效
    用于将已经从非易失性存储器接收到微处理器程序步骤的动态存储器地址空间重新定位到非易失性存储器的地址空间的系统

    公开(公告)号：US5109521A

    公开(公告)日：1992-04-28

    申请号：US477187

    申请日：1990-02-05

    申请人： Paul R. Culley

    发明人： Paul R. Culley

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0638

    摘要： A personal computer transfers the contents of the computer's slow 16 bit read only memory (ROM) into the computer's fast 32 bit random access memory (RAM), remaps the RAM space to include the ROM space and disables the ROM. Portions of the RAM are tested before the contents are transferred. After the transfer the computer operates out of the RAM. Additionally, the RAM address space containing the ROM contents can selectively be made write protected so that the data cannot be changed.

    摘要翻译： 个人电脑将计算机的慢16位只读存储器（ROM）的内容传输到计算机的快速32位随机存取存储器（RAM）中，重新映射RAM空间以包含ROM空间并禁用ROM。 在传送内容之前测试RAM的部分。 传输后，计算机从RAM中运行。 此外，包含ROM内容的RAM地址空间可以选择性地被写入保护，使得数据不能被改变。

    Method for determining cooling requirements of a computer system enclosure
    12.
    发明授权
    Method for determining cooling requirements of a computer system enclosure 有权
    确定计算机系统外壳的冷却要求的方法

    公开(公告)号：US08117012B2

    公开(公告)日：2012-02-14

    申请号：US12213146

    申请日：2008-06-16

    申请人： Wade D. Vinson ,  Paul R. Culley ,  Thomas D. Rhodes

    发明人： Wade D. Vinson ,  Paul R. Culley ,  Thomas D. Rhodes

    IPC分类号： G06F17/50

    CPC分类号： G06F1/20

    摘要： A computer-implemented method is used for determining cooling requirements of a computer system enclosure, where the enclosure includes a number of installed modules, the modules including fan modules. The method includes the steps of determining an individual impedance curve of each installed module; determining fan curves for the installed fan modules; based on the individual impedance curves, determining an overall system impedance curve for the computer system; determining desired performance requirements for the computer system; based on the desired performance requirements, determining corresponding fan curves; and choosing a fan curve that intersects the system impedance curve.

    摘要翻译： 计算机实现的方法用于确定计算机系统机箱的冷却需求，其中机箱包括多个已安装的模块，模块包括风扇模块。 该方法包括以下步骤：确定每个安装的模块的单个阻抗曲线; 确定安装的风扇模块的风扇曲线; 基于各个阻抗曲线，确定计算机系统的整个系统阻抗曲线; 确定计算机系统的期望性能要求; 根据所需的性能要求，确定相应的风扇曲线; 并选择与系统阻抗曲线相交的风扇曲线。

    Reliable datagram transport service
    15.
    发明授权
    Reliable datagram transport service 失效
    可靠的数据报传输服务

    公开(公告)号：US07171484B1

    公开(公告)日：2007-01-30

    申请号：US09980759

    申请日：2000-05-24

    申请人： Michael R. Krause ,  David J. Garcia ,  Paul R. Culley ,  Renato J. Recio ,  Alan F. Benner

    发明人： Michael R. Krause ,  David J. Garcia ,  Paul R. Culley ,  Renato J. Recio ,  Alan F. Benner

    IPC分类号： G06F15/16

    CPC分类号： H04L47/10 ,  G06F9/544 ,  H04L47/18 ,  H04L47/2475 ,  H04L47/34

    摘要： A distributed computer system includes a source endnode including a source process which produces message data and a send work queue having work queue elements that describe the message data for sending. A destination endnode includes a destination process and a receive work queue having work queue elements that describe where to place incoming message data. A communication fabric provides communication between the source endnode and the destination endnode. An end-to-end context is provided at the source endnode and the destination endnode storing state information to ensure the reception and sequencing of message data sent from the source endnode to the destination endnode permitting reliable datagram service between the source endnode and the destination endnode.

    摘要翻译： 分布式计算机系统包括源端节点，其包括产生消息数据的源过程和具有描述用于发送的消息数据的工作队列元素的发送工作队列。 目的地节点包括目的地进程和具有描述入站消息数据的位置的工作队列元素的接收工作队列。 通信结构提供源端节点和目的端节点之间的通信。 在源端节点和目的地端节点提供端到端上下文存储状态信息，以确保从源端节点发送到目的端点的消息数据的接收和排序，从而允许源端节点与目的端节点之间的可靠数据报服务 。

    Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew
    16.
    发明授权
    Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew 有权
    电路和方法采用反馈来驱动时钟信号以补偿负载引起的偏移

    公开(公告)号：US06182236B2

    公开(公告)日：2001-01-30

    申请号：US09140146

    申请日：1998-08-26

    申请人： Paul R. Culley ,  Hung Q. Le

    发明人： Paul R. Culley ,  Hung Q. Le

    IPC分类号： G06F104

    CPC分类号： G06F1/10 ,  H03L7/07 ,  H03L7/087 ,  H03L7/0996

    摘要： A clock generation circuit is provided within an electronic computer system to adjust the phase of a clocking signal provided to various subsystems of the electronic system. A first phase-locked loop (PLL) is provided to establish multiple phases of a first reference clock. One of those phases is selected as a second reference clock, and a second PLL synchronizes the clocking signal to that second reference clock. Each subsystem and associated load which receives the clocking signal has a corresponding clock generation circuit comprising the second PLL. The second PLL for one subsystem can adjust the clocking signal phase prior to that subsystem receiving the clocking signal. The amount by which the second PLL adjusts phase on clocking signal may be different than that by which another, second PLL adjusts the clocking signal arriving on another subsystem. In all instances, however, the clocking signal arriving at the various subsystems are independently and variably changed to match the unique load characteristics of each subsystem using feedback of the clocking signal to the input of each respective second PLL.

    摘要翻译： 时钟生成电路设置在电子计算机系统内，以调整提供给电子系统的各个子系统的时钟信号的相位。 提供第一锁相环（PLL）以建立第一参考时钟的多个相位。 选择其中一个相位作为第二参考时钟，并且第二PLL将时钟信号与该第二参考时钟同步。 接收时钟信号的每个子系统和相关联的负载具有包括第二PLL的对应的时钟产生电路。 一个子系统的第二个PLL可以在子系统接收时钟信号之前调整时钟信号相位。 第二PLL在时钟信号上调整相位的量可能不同于另一个第二PLL调节到达另一个子系统的时钟信号的量。 然而，在所有情况下，到达各个子系统的时钟信号被独立地且可变地改变，以使每个子系统的唯一负载特性使用时钟信号的反馈到每个相应的第二PLL的输入。

    Data error detection and correction
    17.
    发明授权
    Data error detection and correction 失效
    数据错误检测和纠正

    公开(公告)号：US6024486A

    公开(公告)日：2000-02-15

    申请号：US658732

    申请日：1996-06-05

    申请人： Sompong P. Olarig ,  Paul R. Culley ,  Joseph P. Miller

    发明人： Sompong P. Olarig ,  Paul R. Culley ,  Joseph P. Miller

    IPC分类号： G06F11/10 ,  G11C29/00 ,  H03M13/00

    CPC分类号： G06F11/10

    摘要： Data errors on a communications channel in a computer system are corrected. The data is transmitted over the communications channel in a sequence of time-multiplexed phases. A storage device accumulates the phases of data. An error detector and correction device checks the accumulated data for a data error and corrects the data error. The error detection and correction device can correct a one-bit data error, a two-bit data error, and a three-bit data error. Multiple bit errors can be corrected if the multiple bits of data are transmitted over one cable wire in multiple time phases. The communications channel carries the data over N sub-channels, and a parity check generator employs a predetermined parity check matrix based upon the N sub-channels and a probability that multiple errors in the accumulated data are attributable to a faulty sub-channel that affects the same data position in different time phases of the data. The error detection and correction device is operated based upon the parity check matrix. The communications channel includes a cable having N wire pairs, and the N sub-channels include the N wire pairs.

    摘要翻译： 计算机系统中的通信信道上的数据错误得到纠正。 数据通过通信信道以时间复用阶段的顺序发送。 存储设备累积数据的相位。 错误检测器和校正装置检查累积的数据是否存在数据错误，并纠正数据错误。 错误检测和校正装置可以纠正1位数据错误，2位数据错误和3位数据错误。 如果在多个时间阶段通过一根电缆线传输多个数据位，则可以纠正多个位错误。 通信信道通过N个子信道携带数据，并且奇偶校验生成器基于N个子信道采用预定的奇偶校验矩阵，并且累积数据中的多个错误归因于影响到的子信道的错误的概率 在数据的不同时间段内的相同数据位置。 基于奇偶校验矩阵来操作错误检测和校正装置。 通信信道包括具有N线对的电缆，并且N个子信道包括N个线对。

    Double buffering operations between the memory bus and the expansion bus of a computer system
    19.
    发明授权
    Double buffering operations between the memory bus and the expansion bus of a computer system 失效

    公开(公告)号：US5519839A

    公开(公告)日：1996-05-21

    申请号：US956068

    申请日：1992-10-02

    申请人： Paul R. Culley ,  Mark Taylor

    发明人： Paul R. Culley ,  Mark Taylor

    IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F13/40 ,  G06F12/08

    CPC分类号： G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

    摘要： Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.