公开(公告)号：US08117012B2

公开(公告)日：2012-02-14

申请号：US12213146

申请日：2008-06-16

申请人： Wade D. Vinson ,  Paul R. Culley ,  Thomas D. Rhodes

发明人： Wade D. Vinson ,  Paul R. Culley ,  Thomas D. Rhodes

IPC分类号： G06F17/50

CPC分类号： G06F1/20

摘要： A computer-implemented method is used for determining cooling requirements of a computer system enclosure, where the enclosure includes a number of installed modules, the modules including fan modules. The method includes the steps of determining an individual impedance curve of each installed module; determining fan curves for the installed fan modules; based on the individual impedance curves, determining an overall system impedance curve for the computer system; determining desired performance requirements for the computer system; based on the desired performance requirements, determining corresponding fan curves; and choosing a fan curve that intersects the system impedance curve.

摘要翻译： 计算机实现的方法用于确定计算机系统机箱的冷却需求，其中机箱包括多个已安装的模块，模块包括风扇模块。 该方法包括以下步骤：确定每个安装的模块的单个阻抗曲线; 确定安装的风扇模块的风扇曲线; 基于各个阻抗曲线，确定计算机系统的整个系统阻抗曲线; 确定计算机系统的期望性能要求; 根据所需的性能要求，确定相应的风扇曲线; 并选择与系统阻抗曲线相交的风扇曲线。

公开(公告)号：US20080312888A1

公开(公告)日：2008-12-18

申请号：US12213146

申请日：2008-06-16

申请人： Wade D. Vinson ,  Paul R. Culley ,  Thomas D. Rhodes

发明人： Wade D. Vinson ,  Paul R. Culley ,  Thomas D. Rhodes

IPC分类号： G06F17/10

CPC分类号： G06F1/20

摘要： A computer-implemented method is used for determining cooling requirements of a computer system enclosure, where the enclosure includes a number of installed modules, the modules including fan modules. The method includes the steps of determining an individual impedance curve of each installed module; determining fan curves for the installed fan modules; based on the individual impedance curves, determining an overall system impedance curve for the computer system; determining desired performance requirements for the computer system; based on the desired performance requirements, determining corresponding fan curves; and choosing a fan curve that intersects the system impedance curve.

摘要翻译： 计算机实现的方法用于确定计算机系统机箱的冷却需求，其中机箱包括多个已安装的模块，模块包括风扇模块。 该方法包括以下步骤：确定每个安装的模块的单个阻抗曲线; 确定安装的风扇模块的风扇曲线; 基于各个阻抗曲线，确定计算机系统的整个系统阻抗曲线; 确定计算机系统的期望性能要求; 根据所需的性能要求，确定相应的风扇曲线; 并选择与系统阻抗曲线相交的风扇曲线。

公开(公告)号：US07617376B2

公开(公告)日：2009-11-10

申请号：US10641127

申请日：2003-08-14

申请人： Mallikarjun Chadalapaka ,  Dwight L. Barron ,  Paul R. Culley ,  Jeffrey R. Hilland ,  James G. Wendt

发明人： Mallikarjun Chadalapaka ,  Dwight L. Barron ,  Paul R. Culley ,  Jeffrey R. Hilland ,  James G. Wendt

IPC分类号： G06F12/00

CPC分类号： G06F13/4009 ,  G06F12/1081 ,  H04L67/00

摘要： The disclosed embodiments relate to an optimized memory registration mechanism that may comprise an upper layer protocol that associates I/O buffers with memory regions and that manages steering tags. The memory regions may be associated with a translation page table. The upper layer protocol may allocate one of the steering tags associated with at least one of the memory regions for a memory operation.

摘要翻译： 所公开的实施例涉及优化的存储器注册机制，其可以包括将I / O缓冲器与存储器区域相关联并且管理转向标签的上层协议。 存储器区域可以与转换页表相关联。 上层协议可以分配与存储器操作中的至少一个存储器区域相关联的转向标签中的一个。

公开(公告)号：US20080005270A1

公开(公告)日：2008-01-03

申请号：US11669875

申请日：2007-01-31

申请人： Kevin B. Leigh ,  Paul R. Culley

发明人： Kevin B. Leigh ,  Paul R. Culley

IPC分类号： G06F15/16

CPC分类号： H04L67/125 ,  G06F15/16 ,  H04L49/357 ,  H04L49/40

摘要： A method comprises obtaining a value from each of a plurality of memory devices. Each of the values is indicative of a characteristic of a portion of a communication channel. The method further comprises programming a communication device based at least in part on the characteristic.

摘要翻译： 一种方法包括从多个存储器件中的每一个获得一个值。 每个值表示通信信道的一部分的特性。 该方法还包括至少部分地基于该特征对通信设备进行编程。

公开(公告)号：US6032271A

公开(公告)日：2000-02-29

申请号：US658750

申请日：1996-06-05

申请人： Alan L. Goodrum ,  Jeffrey S. Autor ,  Paul R. Culley ,  Joseph P. Miller ,  Siamak Tavallaei ,  Barry P. Basile ,  Elizabeth A. Richard ,  Eric E. Rose

发明人： Alan L. Goodrum ,  Jeffrey S. Autor ,  Paul R. Culley ,  Joseph P. Miller ,  Siamak Tavallaei ,  Barry P. Basile ,  Elizabeth A. Richard ,  Eric E. Rose

IPC分类号： G06F11/30 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34

CPC分类号： G06F11/2005 ,  G06F11/2007 ,  G06F11/2012 ,  G06F11/2221 ,  G06F11/349 ,  G06F11/0757 ,  G06F11/10 ,  G06F11/221

摘要： A device causing a faulty condition in a computer system having devices is isolated by detecting for a faulty condition associated with the devices and identifying the device causing the faulty condition. The devices are coupled to a bus. The faulty condition includes a bus hang condition. The devices are turned off when a bus hang condition is detected. The devices are then turned back on to test the devices. Each device is tested by writing and reading its configuration space. Information on the bus associated with the faulty condition is stored. The stored information is retrieved after the faulty condition has occurred, with the stored information including address, data, and bus control information.

摘要翻译： 在具有设备的计算机系统中导致故障状态的设备通过检测与设备相关联的故障状况并识别导致故障状态的设备而被隔离。 这些设备耦合到总线。 故障状况包括总线挂起状况。 当检测到总线挂起状态时，这些设备被关闭。 然后将设备重新打开以测试设备。 每个设备都通过写入和读取其配置空间进行测试。 存储与故障条件相关的总线上的信息。 存储的信息在故障状态发生后被检索，存储的信息包括地址，数据和总线控制信息。

公开(公告)号：US6000040A

公开(公告)日：1999-12-07

申请号：US739687

申请日：1996-10-29

申请人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

发明人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

IPC分类号： G06F11/22 ,  G06F11/07 ,  G06F11/00

CPC分类号： G06F11/0745 ,  G06F11/0748 ,  G06F11/079

摘要： Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

摘要翻译： 具有电路的计算机系统中的故障由连接的故障检测器来管理，以检测各个电路的故障状态。 故障管理器将故障状态与相应的电路相关联。 故障管理器包括连接到系统管理器以识别哪些电路在计算机系统中导致故障的操作。 与相应电路相关联的故障检测器被配置为检测各个电路的故障操作并产生故障状态信息。 连接中央管理器，从故障检测器累积故障状态信息。 其中一个电路包括总线，故障状态包括总线错误状况。 总线连接到多个设备，故障管理器识别多个设备中的哪一个引起总线错误状况。 其中一个电路包括多个模块，故障管理器识别多个模块的故障状态。 模块包括状态机。 其中一个电路包括内部时钟，并且电路的故障状态包括内部时钟不能正常工作。 其中一个电路包括温度传感器，并且电路的故障状态包括由温度传感器检测的高温条件。

公开(公告)号：US5943482A

公开(公告)日：1999-08-24

申请号：US658602

申请日：1996-06-05

申请人： Paul R. Culley ,  Alan L. Goodrum ,  Raymond Y.L. Chow ,  Barry S. Basile

发明人： Paul R. Culley ,  Alan L. Goodrum ,  Raymond Y.L. Chow ,  Barry S. Basile

IPC分类号： G06F1/26 ,  G06F1/18 ,  G06F12/08 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4081

摘要： A computer system has a bus, a connector for a circuit card, and a clamp configured to selectively prevent removal of the circuit card from the connector when the clamp is engaged. The computer system has circuitry connected to monitor the engagement status of the clamp and to regulate delivery of power to the connector based on the engagement state of the clamp.

摘要翻译： 计算机系统具有总线，用于电路卡的连接器和配置成当夹具接合时选择性地防止从连接器移除电路卡的夹具。 计算机系统具有连接的电路，用于监视夹具的接合状态，并根据夹具的接合状态调节对连接器的电力输送。

公开(公告)号：US5870568A

公开(公告)日：1999-02-09

申请号：US903949

申请日：1997-07-31

申请人： Paul R. Culley ,  Mark Taylor

发明人： Paul R. Culley ,  Mark Taylor

IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F13/40 ,  G06F13/20

CPC分类号： G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

摘要： Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.

公开(公告)号：US5247685A

公开(公告)日：1993-09-21

申请号：US996526

申请日：1992-12-23

申请人： John A. Landry ,  Paul R. Culley

发明人： John A. Landry ,  Paul R. Culley

IPC分类号： G06F13/26

CPC分类号： G06F13/26

摘要： Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

摘要翻译： 两个独立运行的微处理器共享共同的控制，数据和地址总线。 当总线上的第一个微处理器在总线上被分配时，通过在下一个总线周期开始时将中断向量放置在总线上来响应所有可屏蔽的中断。 当第二个微处理器在总线上并且接收到可屏蔽中断时，禁止下一个总线周期的开始，使中断向量放在总线上。

公开(公告)号：US5159679A

公开(公告)日：1992-10-27

申请号：US378579

申请日：1989-07-10

申请人： Paul R. Culley

发明人： Paul R. Culley

IPC分类号： G06F13/28 ,  G06F13/42

CPC分类号： G06F13/4243 ,  G06F13/28

摘要： The present invention is a computer system which can perform master unit controlled memory accesses at a first rate, DMA controlled operations at a second rate and burst operations of both types at a higher third rate. The burst operation is set up by performing a standard access cycle, thus setting up the dynamic random access memory row address, and then performing a series of fast, column address-only accesses to the same page of memory. The fast mode must be exited to a standard rate access whenever a page boundary is crossed, with burst operations recommencing thereafter. Wait states can be inserted in all type operations. Thirty-two bit master units can downshift or step down to 16 bit operation to respond to 16 bit burstable responding units.