公开(公告)号：US6151669A

公开(公告)日：2000-11-21

申请号：US169481

申请日：1998-10-10

申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi ,  Guillermo Juan Rozas

发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi ,  Guillermo Juan Rozas

IPC分类号： G06F7/00 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/30014 ,  G06F9/30094 ,  G06F9/3842

摘要： A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

公开(公告)号：US20120002675A1

公开(公告)日：2012-01-05

申请号：US12827495

申请日：2010-06-30

申请人： MICHAEL KAUSCHKE ,  Gautam B. Doshi

发明人： MICHAEL KAUSCHKE ,  Gautam B. Doshi

IPC分类号： H04L12/56 ,  G06F3/00

CPC分类号： H04L47/826 ,  H04L45/06 ,  H04L47/50 ,  H04L49/00 ,  H04L49/109 ,  H04L49/1584 ,  H04L49/3063 ,  H04L49/90

摘要： In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于确定在节点的输入/输出（I / O）电路中接收的分组是否发往该节点的方法，如果是，则将分组提供给I / O电路并且确定I / O电路的入口队列中是否存在一个或多个分组，并且如果是，则根据与业务流独立的全局调度将选择的分组提供给第一或第二输出寄存器。 描述和要求保护其他实施例。

公开(公告)号：US06820250B2

公开(公告)日：2004-11-16

申请号：US10143163

申请日：2002-05-09

申请人： Kalyan Muthukumar ,  Gautam B. Doshi

发明人： Kalyan Muthukumar ,  Gautam B. Doshi

IPC分类号： G06F944

CPC分类号： G06F8/4452

摘要： A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.

摘要翻译： 提供了一种处理嵌套循环的方法，该嵌套循环在外循环中包括模调度内循环。 嵌套循环调度为执行外循环的给定迭代的内循环的epilog阶段，其中内循环的前序级用于外循环的下一次迭代。 对于本发明的一个实施例，这通过将用于内部循环的epilog计数器初始化为绕过排出软件流水线的值来实现。 这会导致处理器在开始耗尽内循环管线之前退出内循环。 内循环流水线在外循环的下一次迭代期间排出，而内循环流水线填满外循环的下一次迭代。

公开(公告)号：US06578059B1

公开(公告)日：2003-06-10

申请号：US09169669

申请日：1998-10-10

申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

IPC分类号： G06F748

CPC分类号： G06F9/3865 ,  G06F7/483 ,  G06F7/49905 ,  G06F7/49942 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30123 ,  G06F2207/382

摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

公开(公告)号：US06321330B1

公开(公告)日：2001-11-20

申请号：US09322196

申请日：1999-05-28

申请人： Gautam B. Doshi ,  Kalyan Muthukumar

发明人： Gautam B. Doshi ,  Kalyan Muthukumar

IPC分类号： G06F934

CPC分类号： G06F9/383 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/3013 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/384

摘要： The present invention provides a mechanism for prefetching array data efficiently from within a loop. A prefetch instruction is parameterized by a register from a set of rotating registers. On each loop iteration, a prefetch is implemented according to the parameterized prefetch instruction, and the address targeted by the prefetch instruction is adjusted. The registers are rotated for each loop iteration, and the prefetch instruction parameterized by the rotating register is adjusted accordingly. The number of iterations between prefetches for a given array is determined by the number of elements in the set of rotating register.

摘要翻译： 本发明提供了一种用于从循环内有效地预取数组数据的机制。 预取指令由来自一组旋转寄存器的寄存器参数化。 在每个循环迭代中，根据参数化的预取指令实现预取，并且调整由预取指令指定的地址。 对于每个循环迭代，寄存器被旋转，并且相应地调整由旋转寄存器参数化的预取指令。 给定数组的预取之间的迭代次数由旋转寄存器组中的元素数决定。

公开(公告)号：US06301705B1

公开(公告)日：2001-10-09

申请号：US09164327

申请日：1998-10-01

申请人： Gautam B. Doshi ,  Peter Markstein ,  Alan H. Karp ,  Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Michael Morrison

发明人： Gautam B. Doshi ,  Peter Markstein ,  Alan H. Karp ,  Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Michael Morrison

IPC分类号： G06F945

CPC分类号： G06F9/3865 ,  G06F9/3842

摘要： The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.

摘要翻译： 本发明一般涉及用于支持对包括非投机和推测指令的中央处理单元（CPU）的指令集的推测性执行的系统和方法。 根据本发明的一个方面，一种方法包括以下步骤：评估程序的指令以确定各个指令是推测性还是非推测性的，并且评估每个推测性指令以确定其是否产生异常。 对于产生异常的每个推测性指令，该方法然后将延迟异常令牌（DET）编码为CPU的寄存器的未使用的寄存器值。 根据本发明的另一方面，提供了一种系统，该系统包括被配置为评估指令集的指令以确定各个指令是推测性还是非推测性的电路。 系统还包括被配置为评估每个推测性指令以确定其是否产生异常的电路。 最后，系统还包括被配置为将延迟异常令牌（DET）编码为（CPU的）寄存器的未使用寄存器值的电路。