公开(公告)号：US11881484B2

公开(公告)日：2024-01-23

申请号：US18150501

申请日：2023-01-05

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

CPC classification number: H01L27/11807 ,  B82Y10/00 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L2027/11864 ,  H01L2027/11874

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US11574930B2

公开(公告)日：2023-02-07

申请号：US17235603

申请日：2021-04-20

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US11348925B2

公开(公告)日：2022-05-31

申请号：US16711018

申请日：2019-12-11

Applicant: SOCIONEXT INC.

Inventor： Junji Iwahori

IPC: H01L29/06 ,  H01L27/11 ,  B82Y10/00

Abstract: A semiconductor integrated circuit device using nanowire FETs has a circuit block in which a plurality of cell rows each including a plurality of standard cells lined up in the X direction are placed side by side in the Y direction. The plurality of standard cells each include a plurality of nanowires that extend in the X direction and are placed at a predetermined pitch in the Y direction. The plurality of standard cells have a cell height, that is a size in the Y direction, M times (M is an odd number) as large as half the pitch of the nanowires.

公开(公告)号：US11296230B2

公开(公告)日：2022-04-05

申请号：US16931693

申请日：2020-07-17

Applicant: SOCIONEXT INC.

Inventor： Junji Iwahori

IPC: H01L29/786 ,  H01L27/088

Abstract: A semiconductor integrated circuit device provided with vertical nanowire (VNW) FETs includes a tap cell. The tap cell includes a power supply interconnect extending in a first direction and a bottom region of a first conductivity type formed in a top portion of a well or substrate of the first conductivity type. The bottom region overlaps the power supply interconnect as viewed from top and is connected with the power supply interconnect.

公开(公告)号：US12249637B2

公开(公告)日：2025-03-11

申请号：US17706177

申请日：2022-03-28

Applicant: Socionext Inc.

Inventor： Junji Iwahori

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: In a p-type region, a nanosheet farthest from an n-type region has a face exposed from a first gate interconnect on the side away from the n-type region in the Y direction. In the n-type region, a nanosheet farthest from the p-type region has a face exposed from a second gate interconnect on the side away from the p-type region in the Y direction. In the p-type region, a nanosheet closest to the n-type region has a face exposed from the first gate interconnect on the side closer to the n-type region in the Y direction. In the n-type region, a nanosheet closest to the p-type region has a face exposed from the second gate interconnect on the side closer to the p-type region in the Y direction.

公开(公告)号：US12062694B2

公开(公告)日：2024-08-13

申请号：US17889106

申请日：2022-08-16

Applicant: Socionext Inc.

Inventor： Junji Iwahori

IPC: G11C11/00 ,  G11C11/412 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/0673 ,  G11C11/412 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H10B10/12 ,  H01L2027/11881

Abstract: A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.

公开(公告)号：US11563432B2

公开(公告)日：2023-01-24

申请号：US17577701

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Junji Iwahori

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US11387256B2

公开(公告)日：2022-07-12

申请号：US17065875

申请日：2020-10-08

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US11011546B2

公开(公告)日：2021-05-18

申请号：US16881255

申请日：2020-05-22

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US20200335488A1

公开(公告)日：2020-10-22

申请号：US16918852

申请日：2020-07-01

Applicant: SOCIONEXT INC.

Inventor： Junji Iwahori

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: A layout structure of a capacitance cell using vertical nanowire (VNW) FETs is provided. The capacitance cell includes a plurality of first-conductivity type VNW FETs lining up in the X direction, provided between a first power supply interconnect and a second power supply interconnect. The plurality of first-conductivity type VNW FETs include at least one first VNW FET having a top and a bottom connected with the first power supply interconnect and a gate connected with the second power supply interconnect.