公开(公告)号：US06453427B2

公开(公告)日：2002-09-17

申请号：US09224380

申请日：1998-12-31

申请人： Nhon T. Quach ,  John W. C. Fu ,  James O. Hays ,  Valentin Anders ,  Sorin Iacobovici ,  Alberto J. Munoz ,  Dean A. Mulla

发明人： Nhon T. Quach ,  John W. C. Fu ,  James O. Hays ,  Valentin Anders ,  Sorin Iacobovici ,  Alberto J. Munoz ,  Dean A. Mulla

IPC分类号： G06F1100

CPC分类号： G06F11/1044

摘要： An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

摘要翻译： 在计算机系统的数据中检测到不可校正的错误。 允许错误数据存储在计算机系统的第一和第二高速缓存中，同时系统运行第一和第二进程，第一进程与数据相关联。 尝试从缓存加载数据时，第一个进程终止。 同时，第二个过程继续运行。

公开(公告)号：US20190004112A1

公开(公告)日：2019-01-03

申请号：US15636762

申请日：2017-06-29

申请人： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

发明人： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

IPC分类号： G01R31/317 ,  H04L12/26 ,  G01R31/26

摘要： A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

公开(公告)号：US08412981B2

公开(公告)日：2013-04-02

申请号：US11648111

申请日：2006-12-29

申请人： Alberto J. Munoz ,  Sorin Iacobovici

发明人： Alberto J. Munoz ,  Sorin Iacobovici

IPC分类号： G06F11/16 ,  G06F11/00

CPC分类号： G06F11/2028 ,  G06F11/2051

摘要： Methods and apparatus to provide core sparing on multi-core platforms are described. In an embodiment, stored core state information of a target core (e.g., a core that has detected a fault condition (e.g., within its circuitry) or a request to offload operations from the target core (e.g., to enable run-time diagnostics without interfering with system software)) may be read by a spare core which is to operationally replace the target core. Other embodiments are also described.

摘要翻译： 描述了在多核平台上提供核心备用的方法和设备。 在一个实施例中，存储目标核心的核心状态信息（例如，已经检测到故障状况的核心（例如，在其电路内）或从目标核心卸载操作的请求（例如，以启用运行时诊断而没有 干扰系统软件））可以由备用核心读取，备用核心在运行上替代目标核心。 还描述了其它实施例。

公开(公告)号：US07543007B2

公开(公告)日：2009-06-02

申请号：US11209124

申请日：2005-08-22

申请人： Sorin Iacobovici

发明人： Sorin Iacobovici

IPC分类号： G06F7/00

CPC分类号： G06F11/10 ,  G06F5/01 ,  G06F7/72

摘要： Errors in a shift result can be detected with a residue-based mechanism, instead of with duplication of an entire shifter. The commutative property of residue computation over a bit string allows the residue of a value to be independent of the actual bit positions when the divisor is a Merrill number. Without a duplicated shifter, an operand that is the subject of a shift operation is formatted to become a multiple of k, where divisor=2k−1, and the divisor is used for computation of residues. The shift operation is translated to a single position shift or a zero position shift. The translated shift is applied to the formatted operand to generate a shift check value. Despite different values, the residues of the shift result and the shift check value will be the same as long as bit groups are consistent between the two. An error(s) is detected by comparing the residue of the shift check value with the residue of the shift result.

摘要翻译： 可以用基于残余的机制来检测移位结果中的错误，而不是复制整个移位器。 通过比特串进行残差计算的交换属性允许除数为美林数时，值的残差与实际位位置无关。 没有复制的移位器，作为移位操作的对象的操作数被格式化为k的倍数，其中除数= 2k-1，并且除数用于残差的计算。 换档操作转换为单个位置偏移或零位置偏移。 翻译的移位被应用于格式化的操作数以产生移位检查值。 尽管不同的值，只要位组在两者之间是一致的，则移位结果和移位检查值的残差将相同。 通过比较移位检查值的残差与移位结果的残差来检测错误。

公开(公告)号：US06704876B1

公开(公告)日：2004-03-09

申请号：US09669346

申请日：2000-09-26

申请人： Sorin Iacobovici ,  Ronald Melanson

发明人： Sorin Iacobovici ,  Ronald Melanson

IPC分类号： G06F126

CPC分类号： G06F1/206 ,  G06F1/3203

摘要： A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing unit in response to the estimated power dissipation produced by the power estimation circuit.

摘要翻译： 用于中央处理单元的功率耗散控制机构包括：功率估计电路，用于估计在所选择的时间间隔期间由中央处理执行的指令的功耗;以及速度控制器，用于响应于所估计的中心处理单元调整中央处理单元的速度 由功率估计电路产生的功耗。

公开(公告)号：US06185660B2

公开(公告)日：2001-02-06

申请号：US08935681

申请日：1997-09-23

申请人： Dean A. Mulla ,  Sorin Iacobovici

发明人： Dean A. Mulla ,  Sorin Iacobovici

IPC分类号： G06F1200

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F12/0862 ,  G06F12/0875

摘要： An apparatus in a computer, called a pending access queue, for providing data for register load instructions after a cache miss. After a cache miss, when data is available for a register load instruction, the data is first directed to the pending access queue and is provided to an execution pipeline directly from the pending access queue, without requiring the data to be entered in the cache. Entries in the pending access queue include destination register identification, enabling injection of the data into the pipeline during intermediate pipeline phases. The pending access queue provides results to the requesting unit in any order needed, supporting out-of-order cache returns, and provides for arbitration when multiple sources have data ready to be processed. Each separate request to a single line is provided a separate entry, and each entry is provided with its appropriate part of the line as soon as the line is available, thereby rapidly providing data for multiple misses to a single line. The pending access queue may optionally include observability bits, enabling pending releases to complete execution before associated awaited data is present within the pending access queue. The pending access queue may optionally be used to include data to be stored by store instructions that have resulted in a cache miss.

摘要翻译： 计算机中的设备，称为未决访问队列，用于在缓存未命中之后提供用于寄存器加载指令的数据。 在缓存未命中之后，当数据可用于寄存器加载指令时，数据首先被定向到等待访问队列，并且直接从挂起的访问队列提供给执行流水线，而不需要将数据输入缓存。 待处理访问队列中的条目包括目标寄存器标识，可以在中间流水线阶段将数据注入流水线。 待处理的访问队列以所需的任何顺序向请求单元提供结果，支持无序高速缓存返回，并且当多个源具有准备好处理的数据时，提供仲裁。 对单个线路的每个单独请求都提供了单独的条目，并且一旦该线路可用，则每个条目都被提供有线路的适当部分，从而快速向单个线路提供多个未命中的数据。 挂起的访问队列可以可选地包括可观察性位，使等待的版本能够在等待访问队列中存在相关联的等待数据之前完成执行。 等待访问队列可以可选地用于包括由导致高速缓存未命中的存储指令存储的数据。

公开(公告)号：US5860095A

公开(公告)日：1999-01-12

申请号：US582542

申请日：1996-01-02

申请人： Sorin Iacobovici ,  Dean A. Mulla

发明人： Sorin Iacobovici ,  Dean A. Mulla

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0864 ,  G06F12/0897

摘要： A computer memory cache system that includes hardware (called a conflict cache) for short term tolerance and reduction of cache misses and including counters to enable software to detect and remove longer term cache misses through dynamic page remapping. In an example embodiment, when a conflict miss occurs for a low associativity cache, the address of the displaced item is saved in a content addressable memory and the corresponding data is saved in a data RAM. The operating system logically partitions the low associativity cache into bins, where the address range for a bin is a page or multiple pages. Every logical bin in the low associativity cache has a corresponding counter in the conflict cache. Each bin counter counts the number of conflict misses for the corresponding bin. When a bin counter exceeds a predetermined value, the operating system remaps a corresponding page. For a multiple level cache hierarchy, the top level cache is made a subset of the union of a lower level direct mapped cache and the conflict cache. This inclusion property prolongs the life of cache lines in the top level cache in the presence of conflict misses, improving the top level cache performance. In addition, the top level cache (and the conflict cache) may contain several lines that map to the same index in the lower level cache, thereby reducing the probability of thrashing due to the lower level cache.

摘要翻译： 一种计算机存储器高速缓存系统，其包括用于短期容限的硬件（称为冲突高速缓存）和减少高速缓存未命中，并且包括计数器，以使得软件能够通过动态页面重新映射来检测和去除长期高速缓存未命中。 在示例性实施例中，当低关联性高速缓存出现冲突错误时，将移位的项目的地址保存在内容可寻址存储器中，并将相应的数据保存在数据RAM中。 操作系统将低关联缓存逻辑分区成bin，其中bin的地址范围是一页或多页。 低关联性缓存中的每个逻辑bin在冲突高速缓存中都有一个相应的计数器。 每个bin计数器计数相应bin的冲突未命中数。 当柜台计数器超过预定值时，操作系统重新映射对应的页面。 对于多级缓存层次结构，顶级缓存是低级直接映射高速缓存与冲突高速缓存的并集的子集。 这种包含属性在存在冲突缺失的情况下延长了顶级缓存中的高速缓存行的使用寿命，从而提高了顶级缓存的性能。 此外，顶级缓存（和冲突高速缓存）可能包含几条映射到较低级别缓存中相同索引的行，从而降低了由于较低级别缓存引起的颠簸概率。

公开(公告)号：US07418582B1

公开(公告)日：2008-08-26

申请号：US10844931

申请日：2004-05-13

申请人： Sorin Iacobovici ,  Daniel Leibholz ,  David J. Greenhill

发明人： Sorin Iacobovici ,  Daniel Leibholz ,  David J. Greenhill

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30043 ,  G06F9/30127 ,  G06F9/30141 ,  G06F9/30189 ,  G06F9/3851

摘要： A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

摘要翻译： 一种用于优化多线程处理器中的寄存器文件层次结构的方法。 该方法包括提供具有多个寄存器文件单元的寄存器文件层次结构，当处理器以多线程模式操作时，将多个寄存器文件单元与相应的线程相关联，并且当处理器处理器以单线程平坦化多个寄存器文件单元时 以单线程模式运行。 寄存器文件单元对应于多线程处理器的线程。

公开(公告)号：US20080163255A1

公开(公告)日：2008-07-03

申请号：US11648111

申请日：2006-12-29

申请人： Alberto J. Munoz ,  Sorin Iacobovici

发明人： Alberto J. Munoz ,  Sorin Iacobovici

IPC分类号： G06F9/44

CPC分类号： G06F11/2028 ,  G06F11/2051

摘要： Methods and apparatus to provide core sparing on multi-core platforms are described. In an embodiment, stored core state information of a target core (e.g., a core that has detected a fault condition (e.g., within its circuitry) or a request to offload operations from the target core (e.g., to enable run-time diagnostics without interfering with system software)) may be read by a spare core which is to operationally replace the target core. Other embodiments are also described.

摘要翻译： 描述了在多核平台上提供核心备用的方法和设备。 在一个实施例中，存储目标核心的核心状态信息（例如，已经检测到故障状况的核心（例如，在其电路内）或从目标核心卸载操作的请求（例如，以启用运行时诊断而没有 干扰系统软件））可以由备用核心读取，备用核心在运行上替代目标核心。 还描述了其它实施例。

公开(公告)号：US07325101B1

公开(公告)日：2008-01-29

申请号：US11141415

申请日：2005-05-31

申请人： Sorin Iacobovici ,  Paul N. Loewenstein

发明人： Sorin Iacobovici ,  Paul N. Loewenstein

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0897

摘要： Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main memory. By keeping track of the source of cache lines in the on-chip cache memory and by designing the replacement algorithm of the on-chip cache memory such that only one line in a given set maps into an off-cache memory cache line, the frequency of off-chip cache memory accesses may be greatly reduced, thereby improving performance and efficiency.

摘要翻译： 存储在片上高速缓冲存储器中的高速缓存行与一个或多个状态位相关联，该状态位指示存储在高速缓存行中的数据是来自片外高速缓冲存储器还是主存储器。 通过跟踪片上高速缓冲存储器中的高速缓存行的来源，并通过设计片上缓存存储器的替换算法，使得给定集合中只有一行映射到非高速缓存存储器高速缓存行中，频率 的片外高速缓冲存储器访问可能会大大降低，从而提高性能和效率。