-
公开(公告)号：US20190004112A1
公开(公告)日：2019-01-03
申请号：US15636762
申请日：2017-06-29
申请人： Sreejit Chakravarty , Oscar Mendoza , Ramasubramanian Rajamani , Bryan J. Gran , Sorin Iacobovici , Neel Shah , Michael Neve de Mevergnies , John Cruz Mejia , Amy L. Santoni
发明人： Sreejit Chakravarty , Oscar Mendoza , Ramasubramanian Rajamani , Bryan J. Gran , Sorin Iacobovici , Neel Shah , Michael Neve de Mevergnies , John Cruz Mejia , Amy L. Santoni
IPC分类号： G01R31/317 , H04L12/26 , G01R31/26
摘要： A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.
-
2.发明授权Apparatus, system, and method for providing attribute identity control associated with a processor 有权用于提供与处理器相关联的属性标识控制的设备，系统和方法公开(公告)号：US09331855B2
公开(公告)日：2016-05-03
申请号：US13174940
申请日：2011-07-01
申请人： David A. Brown , Adil Karrar , Michael Neve de Mevergnies , Sergiu D. Ghetie , Shahrokh Shahidzadeh
发明人： David A. Brown , Adil Karrar , Michael Neve de Mevergnies , Sergiu D. Ghetie , Shahrokh Shahidzadeh
CPC分类号： H04L9/3234 , G06F21/73 , H04L2209/805
摘要： Described herein are an apparatus, system, and method for attribute identity control in a processor. The apparatus comprises a logic unit including a radio-frequency identification (RFID) tag comprising a non-volatile memory; and a processor operable to access the non-volatile memory, wherein the non-volatile memory for storing an attribute identity associated with a group of processors, the attribute identity being different from an identity of the processor.
摘要翻译： 这里描述了用于处理器中的属性标识控制的装置，系统和方法。 该装置包括一个逻辑单元，该逻辑单元包括一个包括非易失性存储器的射频识别（RFID）标签; 以及可操作以访问所述非易失性存储器的处理器，其中所述非易失性存储器用于存储与一组处理器相关联的属性标识，所述属性标识不同于所述处理器的标识。
-
公开(公告)号：US08590040B2
公开(公告)日：2013-11-19
申请号：US12976523
申请日：2010-12-22
申请人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
发明人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
IPC分类号： G06F21/00
CPC分类号： G06F21/572
摘要： Embodiments of the invention are directed towards logic and/or modules stored in processor secure storage to determine whether a first platform firmware image (e.g., basic input/output system (BIOS), device read-only memory (ROM), manageability engine firmware) loaded onto a processor cache is valid. The processor executes the first platform firmware image if it is determined to be valid. If the first platform image is determined to be invalid, a second platform firmware image is located. If this platform firmware image is determined to be valid, the processor will execute said second platform image.In some embodiments of the invention, the determination of whether the first platform firmware image is valid is based, at least in part, on verification of a digital signature associated with the first platform firmware image. The digital signature may be created, for example, from a private key, wherein the digital signature is verified via a public key.
摘要翻译： 本发明的实施例针对存储在处理器安全存储器中的逻辑和/或模块来确定第一平台固件映像（例如，基本输入/输出系统（BIOS），设备只读存储器（ROM），可管理性引擎固件） 加载到处理器缓存中是有效的。 如果判定为有效，则处理器执行第一平台固件映像。 如果第一平台图像被确定为无效，则定位第二平台固件图像。 如果该平台固件图像被确定为有效，则处理器将执行所述第二平台图像。 在本发明的一些实施例中，确定第一平台固件图像是否有效是至少部分地基于与第一平台固件图像相关联的数字签名的验证。 可以例如从私钥来创建数字签名，其中通过公钥验证数字签名。
-
公开(公告)号：US20150331043A1
公开(公告)日：2015-11-19
申请号：US14279007
申请日：2014-05-15
申请人： Manoj R. Sastry , Enrico D. Carrieri , Michael Neve de Mevergnies , Ioannis T. Schoinas , Michael J. Wiznerowicz
发明人： Manoj R. Sastry , Enrico D. Carrieri , Michael Neve de Mevergnies , Ioannis T. Schoinas , Michael J. Wiznerowicz
IPC分类号： G01R31/3177 , G06F21/76
CPC分类号： G06F21/76 , G01R31/31705 , G01R31/3177 , G06F21/31
摘要： A system on chip (SOC) includes a policy generator to identify lifecycle data that identifies a lifecycle of the SOC and identify authentication data that identifies a particular user that is to debug the SoC. A particular policy is determined based on the lifecycle and identification of the particular user, and policy data is sent to at least one block of the SoC, the policy data identifying the particular policy. Debug access at the block is based on the particular policy.
摘要翻译： 片上系统（SOC）包括一个策略生成器，用于识别识别SOC的生命周期的生命周期数据，并识别识别要调试SoC的特定用户的认证数据。 特定策略基于特定用户的生命周期和标识来确定，策略数据被发送到SoC的至少一个块，该策略数据标识特定策略。 该块的调试访问是基于特定策略。
-
公开(公告)号：US20120167205A1
公开(公告)日：2012-06-28
申请号：US12976523
申请日：2010-12-22
申请人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
发明人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
IPC分类号： G06F21/00
CPC分类号： G06F21/572
摘要： Embodiments of the invention are directed towards logic and/or modules stored in processor secure storage to determine whether a first platform firmware image (e.g., basic input/output system (BIOS), device read-only memory (ROM), manageability engine firmware) loaded onto a processor cache is valid. The processor executes the first platform firmware image if it is determined to be valid. If the first platform image is determined to be invalid, a second platform firmware image is located. If this platform firmware image is determined to be valid, the processor will execute said second platform image.In some embodiments of the invention, the determination of whether the first platform firmware image is valid is based, at least in part, on verification of a digital signature associated with the first platform firmware image. The digital signature may be created, for example, from a private key, wherein the digital signature is verified via a public key.
摘要翻译： 本发明的实施例针对存储在处理器安全存储器中的逻辑和/或模块来确定第一平台固件映像（例如，基本输入/输出系统（BIOS），设备只读存储器（ROM），可管理性引擎固件） 加载到处理器缓存中是有效的。 如果判定为有效，则处理器执行第一平台固件映像。 如果第一平台图像被确定为无效，则定位第二平台固件图像。 如果该平台固件图像被确定为有效，则处理器将执行所述第二平台图像。 在本发明的一些实施例中，确定第一平台固件图像是否有效是至少部分地基于与第一平台固件图像相关联的数字签名的验证。 可以例如从私钥来创建数字签名，其中通过公钥验证数字签名。
-
6.发明申请公开(公告)号：US20100041182A1
公开(公告)日：2010-02-18
申请号：US12604697
申请日：2009-10-23
IPC分类号： H01L21/56
CPC分类号： H05K1/181 , H01L23/585 , H01L2924/0002 , H05K1/0275 , H05K2201/09781 , H05K2201/10159 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , H01L2924/00
摘要： A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.
摘要翻译： 一种方法，装置和系统，该装置在一些实施例中包括印刷电路板（PCB），位于PCB上并电连接到PCB的集成电路（IC），位于PCB和IC之间的芯片，以及 在PCB和IC之间形成封闭的边界屏障并且与PCB接触以限定在内部容纳区域内完全包含芯片的内部容纳区域。
-
7.发明授权公开(公告)号：US07633168B2
公开(公告)日：2009-12-15
申请号：US11476956
申请日：2006-06-28
CPC分类号： H05K1/181 , H01L23/585 , H01L2924/0002 , H05K1/0275 , H05K2201/09781 , H05K2201/10159 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , H01L2924/00
摘要： A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.
摘要翻译： 一种方法，装置和系统，该装置在一些实施例中包括印刷电路板（PCB），位于PCB上并电连接到PCB的集成电路（IC），位于PCB和IC之间的芯片，以及 在PCB和IC之间形成封闭的边界屏障并且与PCB接触以限定在内部容纳区域内完全包含芯片的内部容纳区域。
-
公开(公告)号：US20150058510A1
公开(公告)日：2015-02-26
申请号：US14538941
申请日：2014-11-12
申请人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
发明人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
CPC分类号： G06F13/26 , G06F9/30076 , G06F9/45541 , G06F9/45558 , G06F13/24 , G06F2009/45579 , G06F2213/0058
摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.
摘要翻译： 公开了用于虚拟化中断优先级和传送的处理器，方法和系统的实施例。 在一个实施例中，处理器包括指令硬件和执行硬件。 指令硬件是接收多个指令，包括将处理器从根模式传送到非根模式的第一指令，用于在虚拟机中执行客户软件，其中处理器将根据该模式返回到根模式 检测多个虚拟机退出事件中的任何一个。 执行硬件是执行第一指令，执行第一指令以包括确定第一虚拟处理器优先级值并将第一虚拟处理器优先级值存储在处理器优先级字段的虚拟副本中，其中虚拟副本 处理器优先级字段是对应于与中断控制器相关联的物理资源的虚拟资源。
-
9.发明授权公开(公告)号：US07855102B2
公开(公告)日：2010-12-21
申请号：US12604697
申请日：2009-10-23
CPC分类号： H05K1/181 , H01L23/585 , H01L2924/0002 , H05K1/0275 , H05K2201/09781 , H05K2201/10159 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , H01L2924/00
摘要： A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.
摘要翻译： 一种方法，装置和系统，该装置在一些实施例中包括印刷电路板（PCB），位于PCB上并电连接到PCB的集成电路（IC），位于PCB和IC之间的芯片，以及 在PCB和IC之间形成封闭的边界屏障并且与PCB接触以限定在内部容纳区域内完全包含芯片的内部容纳区域。
-
10.发明申请公开(公告)号：US20080001307A1
公开(公告)日：2008-01-03
申请号：US11476956
申请日：2006-06-28
IPC分类号： H01L23/48
CPC分类号： H05K1/181 , H01L23/585 , H01L2924/0002 , H05K1/0275 , H05K2201/09781 , H05K2201/10159 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , H01L2924/00
摘要： A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.
摘要翻译： 一种方法，装置和系统，该装置在一些实施例中包括印刷电路板（PCB），位于PCB上并电连接到PCB的集成电路（IC），位于PCB和IC之间的芯片，以及 在PCB和IC之间形成封闭的边界屏障并且与PCB接触以限定在内部容纳区域内完全包含芯片的内部容纳区域。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.032 秒)
