公开(公告)号：US20190004112A1

公开(公告)日：2019-01-03

申请号：US15636762

申请日：2017-06-29

申请人： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

发明人： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

IPC分类号： G01R31/317 ,  H04L12/26 ,  G01R31/26

摘要： A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

公开(公告)号：US20160364308A1

公开(公告)日：2016-12-15

申请号：US14737768

申请日：2015-06-12

申请人： Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

发明人： Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

IPC分类号： G06F11/263 ,  G06F11/22

CPC分类号： G06F11/2635 ,  G06F11/1417 ,  G06F11/1433 ,  G06F11/2242 ,  G06F11/2268 ,  G06F11/27

摘要： In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括至少一个核心，功率管理单元，其具有第一测试寄存器，该第一测试寄存器包括第一字段以存储与测试补丁相关联的测试补丁标识符，以及第二字段以存储测试模式指示符以请求核心 功能测试，以及微代码存储器，用于存储由所述至少一个核执行的微代码。 响应于测试补丁标识符，微代码可以根据从固件接口表获得的地址从非易失性存储器访问固件接口表并获得测试补丁。 描述和要求保护其他实施例。

公开(公告)号：US20150089173A1

公开(公告)日：2015-03-26

申请号：US14034813

申请日：2013-09-24

申请人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Michael A. Goldsmith ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H. Smith ,  Ittai Anati ,  Ilya Alexandrovich

发明人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Michael A. Goldsmith ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H. Smith ,  Ittai Anati ,  Ilya Alexandrovich

IPC分类号： G06F12/14 ,  G06F12/08

CPC分类号： G06F12/1408 ,  G06F9/45558 ,  G06F12/0808 ,  G06F12/0897 ,  G06F12/1027 ,  G06F2009/45587 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/152

摘要： Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section are convertible in response to a section conversion instruction.

摘要翻译： 描述了安全的内存重新分区技术。 处理器包括耦合在处理器核心和主存储器之间的处理器核心和存储器控制器。 主存储器包括一个内存范围，包括可转换页面的一部分可转换为安全页面或非安全页面。 响应于页面转换指令的处理器核心是从指令中确定要转换的存储器范围内的可转换页面，并将可转换页面转换为安全页面或非安全页面中的至少一个页面。 存储器范围还可以包括可响应于段转换指令而转换的硬件保留部分。

公开(公告)号：US07849327B2

公开(公告)日：2010-12-07

申请号：US11040261

申请日：2005-01-19

申请人： Hin L. Leung ,  Kushagra V. Vaid ,  Amy L. Santoni ,  Dale Morris ,  Jonathan Ross

发明人： Hin L. Leung ,  Kushagra V. Vaid ,  Amy L. Santoni ,  Dale Morris ,  Jonathan Ross

IPC分类号： G06F11/30 ,  G06F12/14

CPC分类号： G06F9/4812 ,  G06F9/45558 ,  G06F2009/45579

摘要： A technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment. More specifically, embodiments of the invention enable accesses of virtualized I/O resources to be made by guest software without necessarily invoking host software. Furthermore, embodiments of the invention enable more efficient delivery of interrupts to guest software by alleviating the need for host software to be invoked in the delivery process.

摘要翻译： 一种提高虚拟机环境中微处理器的虚拟化输入/输出（I / O）资源的性能的技术。 更具体地，本发明的实施例使得能够由客户软件访问虚拟化I / O资源，而不必调用主机软件。 此外，本发明的实施例通过减轻在传送过程中调用主机软件的需要，可以更有效地将中断传送给客户软件。

公开(公告)号：US20150178226A1

公开(公告)日：2015-06-25

申请号：US14140254

申请日：2013-12-24

申请人： Vincent R. Scarlata ,  Simon P. Johnson ,  Vladimir Beker ,  Jesse Walker ,  Carlos V. Rozas ,  Amy L. Santoni ,  Ittai Anati ,  Raghunandan Makaram ,  Francis X. McKeen ,  Uday R. Savagaonkar

发明人： Vincent R. Scarlata ,  Simon P. Johnson ,  Vladimir Beker ,  Jesse Walker ,  Carlos V. Rozas ,  Amy L. Santoni ,  Ittai Anati ,  Raghunandan Makaram ,  Francis X. McKeen ,  Uday R. Savagaonkar

IPC分类号： G06F12/14

CPC分类号： G06F12/1466 ,  G06F21/74 ,  G06F2212/1052

摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a plurality of processing devices communicatively coupled to the architecturally protected memory, each processing device comprising a first processing logic to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory, or preventing an unauthorized access to the architecturally protected memory; wherein each processing device further comprises a second processing logic to establish a secure communication channel with a second processing device of the processing system, employ the secure communication channel to synchronize a platform identity key representing the processing system, and transmit a platform manifest comprising the platform identity key to a certification system.

摘要翻译： 用于将输出表面位图安全传递到显示引擎的系统和方法。 一个示例处理系统包括：架构受保护的存储器; 以及多个处理设备，通信地耦合到架构保护的存储器，每个处理设备包括第一处理逻辑，以通过执行以下至少一个来实现架构保护的执行环境：执行驻留在架构保护的存储器中的指令，或者防止未授权的 访问架构受保护的内存; 其中每个处理设备还包括第二处理逻辑，用于与所述处理系统的第二处理设备建立安全通信信道，采用所述安全通信信道来同步代表所述处理系统的平台标识密钥，并发送包括所述平台的平台清单 认证系统的身份密钥。

公开(公告)号：US08214830B2

公开(公告)日：2012-07-03

申请号：US11041061

申请日：2005-01-19

申请人： Hin L. Leung ,  Amy L. Santoni ,  Gary N. Hammond ,  William R. Greene ,  Kushagra V. Vaid ,  Dale Morris ,  Jonathan Ross

发明人： Hin L. Leung ,  Amy L. Santoni ,  Gary N. Hammond ,  William R. Greene ,  Kushagra V. Vaid ,  Dale Morris ,  Jonathan Ross

IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F1/24

CPC分类号： G06F9/45533

摘要： Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

摘要翻译： 公开了用于提高虚拟化架构中的性能的装置和方法的实施例。 在一个实施例中，一种装置包括处理器和处理器抽象层。 处理器抽象层包括当由处理器执行时支持技术来提高虚拟化架构中的设备的性能的指令。

公开(公告)号：US20190095350A1

公开(公告)日：2019-03-28

申请号：US15714217

申请日：2017-09-25

申请人： David M. Durham ,  Siddhartha Chhabra ,  Amy L. Santoni ,  Gilbert Neiger ,  Barry E. Huntley ,  Hormuzd M. Khosravi ,  Baiju V. Patel ,  Ravi L. Sahita ,  Gideon Gerzon ,  Ido Ouziel ,  Ioannis T. Schoinas ,  Rajesh M. Sankaran

发明人： David M. Durham ,  Siddhartha Chhabra ,  Amy L. Santoni ,  Gilbert Neiger ,  Barry E. Huntley ,  Hormuzd M. Khosravi ,  Baiju V. Patel ,  Ravi L. Sahita ,  Gideon Gerzon ,  Ido Ouziel ,  Ioannis T. Schoinas ,  Rajesh M. Sankaran

IPC分类号： G06F12/14 ,  G06F21/60 ,  G06F21/82 ,  G06F3/06

摘要： In one embodiment, a cryptographic circuit is adapted to receive a data line including at least an encrypted portion from a memory in response to a read request having a memory address from a first agent, obtain a key identifier for a key of the first agent from the data line, obtain the key using the key identifier, decrypt the at least encrypted portion of the data line using the key and send decrypted data of the at least encrypted portion of the data line to the first agent. Other embodiments are described and claimed.

公开(公告)号：US20170024573A1

公开(公告)日：2017-01-26

申请号：US14803956

申请日：2015-07-20

申请人： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

发明人： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

IPC分类号： G06F21/62 ,  G06F21/60

CPC分类号： G06F21/62 ,  G06F21/602 ,  G06F21/64 ,  G06F21/78 ,  G06F2221/2113

摘要： A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

摘要翻译： 公开了一种实现用于支持存储器地址范围的可配置安全级别的技术的处理器。 在一个实施例中，处理器包括处理核心，存储器控制器，可操作地耦合到处理核心，以访问片外存储器中的数据和可操作地耦合到存储器控制器的存储器加密引擎（MEE）。 所述MEE响应于检测相对于与所述片外存储器相关联的存储器地址范围内的存储器地址识别的存储器位置的存储器访问操作，基于存储的值来识别与所述存储器位置相关联的安全级别指示符 在安全范围寄存器上。 鉴于安全级别指示符，MEE进一步访问与片外存储器的存储器地址范围相关联的数据项的至少一部分。

公开(公告)号：US20120240116A1

公开(公告)日：2012-09-20

申请号：US13483307

申请日：2012-05-30

申请人： Hin L. Leung ,  Amy L. Santoni ,  Gary N. Hammond ,  William R. Greene ,  Kushagra V. Vaid ,  Dale Morris ,  Jonathan Ross

发明人： Hin L. Leung ,  Amy L. Santoni ,  Gary N. Hammond ,  William R. Greene ,  Kushagra V. Vaid ,  Dale Morris ,  Jonathan Ross

IPC分类号： G06F9/455 ,  G06F9/46

CPC分类号： G06F9/45533

摘要： Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

摘要翻译： 公开了用于提高虚拟化架构中的性能的装置和方法的实施例。 在一个实施例中，一种装置包括处理器和处理器抽象层。 处理器抽象层包括当由处理器执行时支持技术来提高虚拟化架构中的设备的性能的指令。