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公开(公告)号：US08707013B2
公开(公告)日：2014-04-22
申请号：US12835320
申请日：2010-07-13
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/381 , G06F9/3822
摘要： In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.
摘要翻译： 根据至少一些实施例，数字信号处理器（DSP）包括与指令获取单元通信的指令获取单元和指令解码单元。 DSP还包括与指令解码单元通信的寄存器组和多个工作单元。 寄存器集包括多个传统谓词寄存器。 与传统谓词寄存器分离，选择性地发送多个按需谓词寄存器，而不改变DSP的操作码空间。
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12.发明授权Upgrade of low priority prefetch requests to high priority real requests in shared memory controller 有权将低优先级预取请求升级到共享内存控制器中的高优先级实际请求公开(公告)号：US08683134B2
公开(公告)日：2014-03-25
申请号：US12356308
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.
摘要翻译： 当实际读取访问请求与先前的预取请求相同时，预取控制器实现升级。 响应每存储器存储器逻辑将预取请求的优先级提升为读取请求的优先级。 如果预取请求仍在等待赢得仲裁，则此优先级升级增加了获取访问的可能性通常会降低延迟。 如果预取请求已经通过仲裁获得访问权限，则升级不起作用。 因此，当对相同地址进行低优先级推测预取时，这通常降低了完成高优先级实际请求时的等待时间。
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公开(公告)号：US20090249106A1
公开(公告)日：2009-10-01
申请号：US12356294
申请日：2009-01-20
申请人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
发明人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.
摘要翻译： 基于硬件的唤醒方案在正常访问掉电存储器时启动内存上电。 触发上电的访问被缓冲。 进一步的访问停止，直到内存完全通电。 然后，缓冲的访问进行到存储器，并且处理器被摆脱失速。 在软件不直接控制访问存储器（例如高速缓存未命中）的情况下，该方案避免了由于访问掉电存储器而导致的不期望的状况。
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公开(公告)号：US06819684B1
公开(公告)日：2004-11-16
申请号：US09713737
申请日：2000-11-15
申请人： Joseph R. Zbiciak
发明人： Joseph R. Zbiciak
IPC分类号： H04J306
CPC分类号： H04J3/073
摘要： A data communications subsystem (15) including a digital signal processor (DSP) (20) for performing bit insertion to preclude the inadvertent serial transmission of a protocol flag sequence is disclosed. A trigger sequence detection process (40) applies an infinite impulse response (IIR) filter to a current sequence of the input bitstream to generate a insertion bitstream that is bit sychronized with the the input bitstream. A bit insertion process (50) then inserts bits into the input bitstream at bit positions indicated by the insertion bitstream. The trigger sequence detection process (40) may be applied to subsequent sections of the input bitstream, as it is not dependent upon the results of the bit insertion process (50).
摘要翻译： 公开了一种数据通信子系统（15），其包括用于执行位插入的数字信号处理器（DSP）（20）以排除协议标志序列的无意串行传输。 触发序列检测处理（40）将无限脉冲响应（IIR）滤波器应用于输入比特流的当前序列，以产生与输入比特流进行比特同步的插入比特流。 然后，位插入处理（50）在插入比特流指示的比特位置处将比特插入到输入比特流中。 触发序列检测处理（40）可以应用于输入比特流的后续部分，因为它不依赖于比特插入处理（50）的结果。
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公开(公告)号：US06453405B1
公开(公告)日：2002-09-17
申请号：US09703179
申请日：2000-10-31
申请人： David Hoyle , Joseph R. Zbiciak
发明人： David Hoyle , Joseph R. Zbiciak
IPC分类号： G06F1200
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30145 , G06F9/30167 , G06F9/3552 , G06F9/3555 , G06F9/3824 , G06F9/3828 , G06F9/3853 , G06F9/3885
摘要： A data processing system having a central processing unit (CPU) with address generation circuitry for accessing a circular buffer region in a non-aligned manner is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory ports. A data transfer address for each load/store instruction is formed by fetching the instruction (600), decoding the instruction (610) to determine instruction type, transfer data size, addressing mode and scaling selection. For a non-aligned instruction, after selectively scaling (620) an offset provided by the instruction and combining the selectively scaled offset with a base address value the resultant address is then augmented (640) by a line size associated with the instruction. For circular addressing mode, both the resultant address and the augmented address are bounded (650, 651) to stay within the circular buffer region and two aligned data items are accessed in parallel (652, 653) and a non-aligned data item is extracted (654) from the two aligned data items, such that the non-aligned data item wraps around the boundary of the circular buffer region.
摘要翻译： 提供一种具有中央处理单元（CPU）的数据处理系统，其具有用于以非对准方式访问循环缓冲区域的地址产生电路。 CPU具有针对密集数值算法处理进行了优化的指令集体系结构。 CPU具有连接到存储器控制器的双存储器端口的双重加载/存储单元。 CPU可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 CPU还可以通过执行利用两个存储器端口的不对齐的加载/存储指令来执行具有四字节或八字节长度的单个非对齐数据传输。 通过取指令（600），解码指令（610）来确定指令类型，传输数据大小，寻址模式和缩放选择，形成每个加载/存储指令的数据传输地址。 对于非对准指令，在选择性地缩放（620）由指令提供的偏移量并且将选择性缩放的偏移量与基址值组合之后，然后将所得到的地址通过与该指令相关联的行大小增大（640）。 对于循环寻址模式，结果地址和扩充地址都被界定（650,651）以保持在循环缓冲区内，并且并行访问两个对齐的数据项（652,653），并且提取不对齐的数据项 （654），使得不对齐的数据项围绕循环缓冲区的边界卷绕。
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公开(公告)号：US08683133B2
公开(公告)日：2014-03-25
申请号：US12356303
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.
摘要翻译： 与先前的预取请求相关联的来自CPU到同一存储体的实际请求将与杀死信号一起发送到每存储器存储体逻辑以终止预取请求。 这避免了在将实际请求发送到同一个存储体之前等待预取请求完成。 杀死信号禁止任何完成预取请求的确认。 当对同一存储体中的不同地址的低优先级推测请求已经被分派时，本发明减少了完成高优先级实际请求的等待时间。
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公开(公告)号：US20090249105A1
公开(公告)日：2009-10-01
申请号：US12356274
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.
摘要翻译： 本发明管理多处理器系统中的共享存储器的掉电和唤醒。 每个共享存储器的寄存器具有与每个主器件相对应的位。 当主机要关闭存储器时，它将其相应的位置于寄存器中。 如果任何处理器信号为存储体供电，则存储器组件的硬件掉电控制器为存储体供电。 存储器的硬件掉电控制器只有在所有处理器信号使存储器电源断电的情况下才能关闭存储器。 在启动存储器掉电之前，等待所有主机在寄存器中设置相应的位。 在任何处理器上运行的软件具有独立于其他处理器的共享存储器的视图，并且不需要处理器间通信。
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18.发明申请Upgrade of Low Priority Prefetch Requests to High Priority Real Requests in Shared Memory Controller 有权将低优先级预取请求升级到共享内存控制器中的高优先级实时请求公开(公告)号：US20090248992A1
公开(公告)日：2009-10-01
申请号：US12356308
申请日：2009-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.
摘要翻译： 当实际读取访问请求与先前的预取请求相同时，预取控制器实现升级。 响应每存储器存储器逻辑将预取请求的优先级提升为读取请求的优先级。 如果预取请求仍在等待赢得仲裁，则此优先级升级增加了获取访问的可能性通常会降低延迟。 如果预取请求已经通过仲裁获得访问权限，则升级不起作用。 因此，当对相同地址进行低优先级推测预取时，这通常降低了完成高优先级实际请求时的等待时间。
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19.发明授权Direct memory access channel controller with quick channels, event queue and active channel memory protection 有权直接内存访问通道控制器，具有快速通道，事件队列和主动通道内存保护公开(公告)号：US07546391B2
公开(公告)日：2009-06-09
申请号：US11383045
申请日：2006-05-12
IPC分类号： G06F13/28 , G06F13/36 , G06F15/167 , G06F12/00
CPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.
摘要翻译： 数据传送控制装置包括通道控制器和传送控制器。 通道控制器接收，优先排序和排队触发控制传输控制器的数据传输请求的事件信号和预定的存储器写入。 事件队列存储映射到存储数据传输参数的参数存储单元的事件号。 映射表和参数存储器可通过存储器映射写操作进行写入。 存储器保护寄存器存储表示允许的数据访问存储器映射的数据。
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公开(公告)号：US06574724B1
公开(公告)日：2003-06-03
申请号：US09702474
申请日：2000-10-31
IPC分类号： G06F1200
CPC分类号： G06F9/3828 , G06F9/30181 , G06F9/3555
摘要： A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value. The resultant address is then provided to the memory system to initiate a data transfer.
摘要翻译： 提供具有中央处理（CPU）单元和操作方法的数据处理系统。 CPU具有针对密集数值算法处理进行了优化的指令集体系结构。 CPU具有连接到存储器控制器的双存储器目标端口的双重加载/存储单元。 CPU可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 CPU还可以通过执行利用两个存储器目标端口的不对齐的加载/存储指令来执行长度为四字节或八字节的单个非对齐数据传输。 每个加载/存储指令的数据传输地址通过取指令，解码指令来确定指令类型，传输数据大小和缩放选择来形成，选择性地缩放由指令提供的偏移量，并将选择性缩放的偏移量与基数 地址值。 然后将结果地址提供给存储器系统以发起数据传送。
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