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    Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions
    11.
    发明授权
    Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions 失效
    绝缘体上半导体器件（SOI）器件，具有超导源极/漏极结

    公开(公告)号：US06465847B1

    公开(公告)日：2002-10-15

    申请号：US09878614

    申请日：2001-06-11

    申请人： Srinath Krishnan ,  Witold P. Maszara

    发明人： Srinath Krishnan ,  Witold P. Maszara

    IPC分类号： H01L2701

    CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/78621

    摘要： A semiconductor-on-insulator (SOI) device. The SOI device includes a semiconductor substrate layer; an insulator layer disposed on the substrate layer; a semiconductor active region disposed on the insulator layer, the active region including a source, a drain, and a body disposed therebetween, at least one of the source and the drain forming a hyperabrupt junction with the body; and a gate disposed on the body such that the gate, source, drain and body are operatively arranged to form a transistor. The at least one of the source and drain forming the hyperabrupt junction with the body includes a silicide region. The silicide region has a generally vertical interface, which is laterally spaced apart from the hyperabrupt junction by about 60 Å to about 150 Å.

    摘要翻译： 绝缘体上半导体（SOI）器件。 SOI器件包括半导体衬底层; 设置在所述基板层上的绝缘体层; 设置在所述绝缘体层上的半导体有源区，所述有源区包括源极，漏极和设置在其间的主体，所述源极和漏极中的至少一个与所述主体形成超级连接; 以及设置在所述主体上的门，使得所述栅极，源极，漏极和主体被可操作地布置以形成晶体管。 与主体形成超破裂结的源极和漏极中的至少一个包括硅化物区域。 硅化物区域具有大致垂直的界面，其与超破裂结交叉横向间隔约60埃至约150埃。

    Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions
    12.
    发明授权
    Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions 失效
    制造绝缘体上半导体（SOI）器件的方法，其具有过度的源极/漏极结

    公开(公告)号：US06429054B1

    公开(公告)日：2002-08-06

    申请号：US09878791

    申请日：2001-06-11

    申请人： Srinath Krishnan ,  Witold P. Maszara

    发明人： Srinath Krishnan ,  Witold P. Maszara

    IPC分类号： H01L2100

    CPC分类号： H01L29/66772 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/458 ,  H01L29/665 ,  H01L29/78621

    摘要： A method of forming a semiconductor-on-insulator (SOI) device. The method includes providing an SOI wafer having an active layer, a substrate and a buried insulator layer therebetween; defining an active region in the active layer; forming a source, a drain and body in the active region, the source and the drain forming respective hyperabrupt junctions with the body, the hyperabrupt junctions being formed by an SPE process which includes amorphizing the at least one of the source and the drain, implanting dopant ion species and recrystalizing at temperature of less than 700° C.; forming a gate disposed on the body such that the source, drain, body and gate are operatively arranged to form a transistor; and forming a silicide region in each of the source and the drain, the silicide regions being spaced from the respective hyperabrupt junctions by a lateral distance of less than about 100 Å.

    摘要翻译： 一种形成绝缘体上半导体（SOI）器件的方法。 该方法包括提供具有有源层，衬底和其间的掩埋绝缘体层的SOI晶片; 在有源层中限定有源区; 在有源区域中形成源极，漏极和主体，源极和漏极与主体形成相应的过度连接点，超破裂结由SPE工艺形成，其包括将源极和漏极中的至少一个非晶化，植入 掺杂剂离子种类，并在低于700℃的温度下重结晶; 形成设置在所述主体上的栅极，使得所述源极，漏极，主体和栅极可操作地布置以形成晶体管; 并且在源极和漏极的每一个中形成硅化物区域，硅化物区域与相应的超破裂接合部分间隔小于约100A的横向距离。

    Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects
    13.
    发明授权
    Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects 有权
    制造MOSFET器件结构的方法，其有助于缓解结电容和浮体效应

    公开(公告)号：US06204138B1

    公开(公告)日：2001-03-20

    申请号：US09260821

    申请日：1999-03-02

    申请人： Srinath Krishnan ,  Witold P. Maszara ,  Ming-Ren Lin

    发明人： Srinath Krishnan ,  Witold P. Maszara ,  Ming-Ren Lin

    IPC分类号： H01L21336

    CPC分类号： H01L29/78612 ,  H01L29/78621

    摘要： A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.

    摘要翻译： 提供了一种形成MOSFET器件的方法。 形成第一轻掺杂区域，第一轻掺杂区域包括器件的LDD延伸区域。 第二非常轻掺杂的区域至少部分地形成在第一轻掺杂区域的下方，第二非常轻掺杂的区域具有小于第一轻掺杂区域的掺杂剂浓度，并且第二极轻掺杂区域以较高能量 水平比第一轻掺杂区域。

    Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile
    15.
    发明授权
    Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile 有权
    形成具有浅突变逆向掺杂剂分布的MOSFET晶体管的方法

    公开(公告)号：US06184112B2

    公开(公告)日：2001-02-06

    申请号：US09204998

    申请日：1998-12-02

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    IPC分类号： H01L21425

    CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/105 ,  H01L29/66545

    摘要： In accordance with the present invention, an amorphous layer is formed in a crystalline substrate (e.g., the channel region of a MOSFET transistor) by, for example, implanting ions of an inert specie such as germanium. A dopant is implanted so that it overlaps with the amorphous layer. Subsequently, low temperature recrystallization of the amorphous layer leads to an abrupt retrograded layer of active dopant in the channel region of the MOSFET. This retrograded dopant layer could be formed before or after the formation of the gate electrode.

    摘要翻译： 根据本发明，通过例如注入诸如锗的惰性物质的离子，在晶体衬底（例如，MOSFET晶体管的沟道区）中形成非晶层。 注入掺杂剂使其与非晶层重叠。 随后，非晶层的低温重结晶导致在MOSFET的沟道区域中的有源掺杂剂的突然退化层。 可以在形成栅电极之前或之后形成该退化的掺杂剂层。

    METHODS OF FORMING DIFFERENT FINFET DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND INTEGRATED CIRCUIT PRODUCTS CONTAINING SUCH DEVICES
    16.
    发明申请
    METHODS OF FORMING DIFFERENT FINFET DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND INTEGRATED CIRCUIT PRODUCTS CONTAINING SUCH DEVICES 有权
    形成具有不同阈值电压的不同FINFET器件的方法和包含这些器件的集成电路产品

    公开(公告)号：US20140070322A1

    公开(公告)日：2014-03-13

    申请号：US13613508

    申请日：2012-09-13

    申请人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

    发明人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

    IPC分类号： H01L21/20 ,  H01L27/088

    CPC分类号： H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

    摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

    摘要翻译： 本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后 形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

    METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS
    17.
    发明申请
    METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS 有权
    用替代通道材料形成FINFET器件的方法

    公开(公告)号：US20140011341A1

    公开(公告)日：2014-01-09

    申请号：US13544259

    申请日：2012-07-09

    申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

    发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

    IPC分类号： H01L21/20

    CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/785

    摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

    摘要翻译： 一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分 并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定 空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面 绝缘材料在第三部分的上表面下方。

    Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate
    20.
    发明授权
    Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate 有权
    形成具有晶体管本体与衬底的直接接触的伪SOI结构的方法

    公开(公告)号：US06245636B1

    公开(公告)日：2001-06-12

    申请号：US09421639

    申请日：1999-10-20

    申请人： Witold P. Maszara

    发明人： Witold P. Maszara

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232 ,  H01L21/76264

    摘要： A method for processing a semiconductor wafer transforms the wafer into one which has a plurality of surface semiconductor platforms for formation of integrated circuit elements thereupon. The platforms are connected to a subsurface bulk layer of semiconductor material via integrally-formed bridges of semiconductor material. The platforms are otherwise surrounded with an electrically-insulating material, thereby providing good insulation between adjacent of the platforms. The method includes the steps of placing a mask on a wafer surface of the wafer, forming a subsurface altered material beneath portions of the wafer surface not covered by the mask, creating exposure openings through the wafer surface to expose a portion of the subsurface altered material, selectively removing the subsurface altered material by selective etching, and filling the subsurface regions and the exposure openings with an electrically-insulating material. In an exemplary embodiment the mask includes a plurality of gate conductors. The wafer surface is bombarded with boron ions to create a subsurface boron-doped material, and the boron-doped material is removed using an appropriate selective etchant.

    摘要翻译： 用于处理半导体晶片的方法将晶片转换为具有用于形成集成电路元件的多个表面半导体平台的晶片。 平台通过半导体材料的整体形成的桥连接到半导体材料的地下体层。 平台另外被电绝缘材料包围，从而在相邻的平台之间提供良好的绝缘。 该方法包括以下步骤：将掩模放置在晶片的晶片表面上，在未被掩模覆盖的晶片表面的部分下方形成次表面改变的材料，从而产生通过晶片表面的暴露开口以暴露部分地下改质材料 通过选择性蚀刻选择性地去除地下改变的材料，并用电绝缘材料填充地下区域和曝光开口。 在示例性实施例中，掩模包括多个栅极导体。 用硼离子轰击晶片表面以产生地下硼掺杂材料，并且使用合适的选择性蚀刻剂去除硼掺杂材料。