公开(公告)号：US09564367B2

公开(公告)日：2017-02-07

申请号：US13613508

申请日：2012-09-13

申请人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

发明人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC分类号： H01L21/8234 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

摘要翻译： 本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后 形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

公开(公告)号：US08580642B1

公开(公告)日：2013-11-12

申请号：US13476645

申请日：2012-05-21

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66795

摘要： One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

摘要翻译： 本文公开的一种说明性方法包括通过图案化的硬掩模层执行第一蚀刻工艺，以在衬底中限定多个间隔开的沟槽，其限定用于器件的鳍片的第一部分，在沟槽中形成绝缘材料层 以及对所述绝缘材料层进行平坦化处理以暴露所述图案化的硬化物，执行第二蚀刻工艺以去除所述硬掩模层并且在所述绝缘材料层内限定空腔，在所述空腔内形成所述翅片的第二部分 ，其中所述翅片的第二部分由与所述基板不同的半导体材料构成，并且对所述绝缘材料层进行第三蚀刻工艺，使得所述绝缘材料的上表面在所述第二部分的上表面下方 鳍的一部分。

公开(公告)号：US20140070322A1

公开(公告)日：2014-03-13

申请号：US13613508

申请日：2012-09-13

申请人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

发明人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC分类号： H01L21/20 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

摘要翻译： 本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后 形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

公开(公告)号：US20140011341A1

公开(公告)日：2014-01-09

申请号：US13544259

申请日：2012-07-09

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

摘要翻译： 一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分 并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定 空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面 绝缘材料在第三部分的上表面下方。

公开(公告)号：US08673718B2

公开(公告)日：2014-03-18

申请号：US13544259

申请日：2012-07-09

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/335

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

摘要翻译： 一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分 并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定 空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面 绝缘材料在第三部分的上表面下方。

公开(公告)号：US20130309847A1

公开(公告)日：2013-11-21

申请号：US13476645

申请日：2012-05-21

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/20

CPC分类号： H01L29/66795

摘要： One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

摘要翻译： 本文公开的一种说明性方法包括通过图案化的硬掩模层执行第一蚀刻工艺，以在衬底中限定多个间隔开的沟槽，其限定用于器件的鳍片的第一部分，在沟槽中形成绝缘材料层 以及对所述绝缘材料层进行平坦化处理以暴露所述图案化的硬化物，执行第二蚀刻工艺以去除所述硬掩模层并且在所述绝缘材料层内限定空腔，在所述空腔内形成所述翅片的第二部分 ，其中所述翅片的第二部分由与所述基板不同的半导体材料构成，并且对所述绝缘材料层进行第三蚀刻工艺，使得所述绝缘材料的上表面在所述第二部分的上表面下方 鳍的一部分。

公开(公告)号：US08010591B2

公开(公告)日：2011-08-30

申请号：US11804893

申请日：2007-05-21

申请人： Mohammad M. Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

发明人： Mohammad M. Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

IPC分类号： G06E3/00

CPC分类号： G06G7/16

摘要： A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

摘要翻译： 使用四个G4-FET的差分输出模拟乘法器电路，每个源极连接到电流源。 四个G4-FET可以分成两对，每对两个G4-FET，其中一对具有连接到负载的漏极，另一对的漏极连接到另一个负载。 差分输出电压在两个负载下进行。 在一个实施例中，对于每个G4-FET，第一和第二结门各自连接在一起，其中第一输入电压施加到每对的前门，并且第二输入电压施加到每个的第一结门 对。 描述和要求保护其他实施例。

公开(公告)号：US20120007052A1

公开(公告)日：2012-01-12

申请号：US12831839

申请日：2010-07-07

申请人： Christopher C. Hobbs ,  Kerem Akarvardar ,  Injo OK

发明人： Christopher C. Hobbs ,  Kerem Akarvardar ,  Injo OK

IPC分类号： H01L27/092 ,  H01L29/775 ,  H01L21/8238

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

摘要： An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor includes a first group of nanowires made of silicon. The nanowire FET device may also include a second transistor on the same substrate, where the second transistor includes a second group of nanowires made of silicon-germanium.

摘要翻译： 提出了一种双通道FET器件的装置，系统和方法。 在一些实施例中，纳米线FET器件可以包括衬底上的第一晶体管，其中第一晶体管包括由硅制成的第一组纳米线。 纳米线FET器件还可以包括在同一衬底上的第二晶体管，其中第二晶体管包括由硅 - 锗制成的第二组纳米线。

公开(公告)号：US07514964B2

公开(公告)日：2009-04-07

申请号：US11377935

申请日：2006-03-15

申请人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad M. Mojarradi ,  Nikzad Toomarian

发明人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad M. Mojarradi ,  Nikzad Toomarian

IPC分类号： H03K19/20 ,  G11C7/00

CPC分类号： H01L29/785 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2029/7857

摘要： An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

摘要翻译： 公开了一种基于G4-FET技术的通用和可编程逻辑门，从而设计出更高效的逻辑电路。 还介绍了一种基于G4-FET的全加器设计。 G4-FET还可以作为独特的路由器设备，提供彼此隔离和垂直的信号路径的共面交叉。 这有可能克服VLSI设计中的复杂互连方案变得越来越成问题的主要限制。

公开(公告)号：US20080001658A1

公开(公告)日：2008-01-03

申请号：US11804893

申请日：2007-05-21

申请人： Mohammad Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

发明人： Mohammad Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

IPC分类号： H99Z99/00

CPC分类号： G06G7/16

摘要： A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

摘要翻译： 一个差分输出模拟乘法器电路，利用四个四极管，每个源极连接到电流源。 四个G 4 SFET可以被分组成两对两个两个G 4 -FET，其中一对具有连接到负载的漏极，另一对具有 其下水道连接到另一个负载。 差分输出电压在两个负载下进行。 在一个实施例中，对于每个G 4 -FET，第一和第二结门各自连接在一起，其中第一输入电压施加到每对的前栅极，第二输入电压为 应用于每对的第一个结门。 描述和要求保护其他实施例。