公开(公告)号：US06908227B2

公开(公告)日：2005-06-21

申请号：US10227125

申请日：2002-08-23

申请人： Stefan Rusu ,  Simon M. Tam

发明人： Stefan Rusu ,  Simon M. Tam

IPC分类号： G01K1/02 ,  G01K7/42 ,  G06F1/20 ,  G01K13/00 ,  G06F1/32

CPC分类号： G06F1/206 ,  G01K1/026 ,  G01K7/42 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.

摘要翻译： 描述了一种用于管理具有多核微处理器的集成电路的温度的装置。 具体来说，热传感器放置在每个微处理器核心的潜在热点。 热管理单元监视热传感器。 如果热传感器识别热点，则热管理单元相应地调整该微处理器核心的工作频率和电压。

公开(公告)号：US06788156B2

公开(公告)日：2004-09-07

申请号：US10456660

申请日：2003-06-06

申请人： Simon M. Tam ,  Stefan Rusu

发明人： Simon M. Tam ,  Stefan Rusu

IPC分类号： H03B2800

CPC分类号： G06F1/324 ,  G06F1/3203 ,  H03L7/06 ,  H03L7/0805 ,  Y02D10/126

摘要： A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

摘要翻译： 一种在处理器中动态地改变时钟频率的方法。 一个实施例的方法包括用来自相位锁定环（PLL）的时钟输出来驱动时钟分配网络。 可调时钟发生器与锁相环锁定。 可调时钟发生器代替时钟分配网络上的PLL。

公开(公告)号：US6092212A

公开(公告)日：2000-07-18

申请号：US996305

申请日：1997-12-22

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： G06F13/40 ,  G06F1/04

CPC分类号： G06F13/4072

摘要： A method and strobe circuit are provided for maintaining a strobe signal at a valid voltage level. The method includes driving the strobe signal at the valid voltage level using a first strobe driver, pre-driving the strobe signal at the valid voltage level using a second strobe driver while the first strobe driver is driving, and terminating the driving of the first strobe driver. The strobe circuit includes a strobe line, a first strobe driver having a first enable input for enabling the first strobe driver and adapted to drive the strobe line with a first strobe signal, and a second strobe driver having a second enable input for enabling the second strobe driver and adapted to drive the strobe line with a second strobe signal. A first strobe controller is coupled to the second enable input and adapted to enable the second strobe driver to pre-drive the second strobe signal while the first strobe driver is enabled, wherein the first and second strobe signals are at equal logic levels.

摘要翻译： 提供了一种用于将选通信号保持在有效电压电平的方法和选通电路。 该方法包括使用第一选通驱动器以有效电压电平驱动选通信号，在第一选通驱动器正在驱动时，使用第二选通驱动器以有效电压电平预驱动选通信号，并终止第一选通脉冲的驱动 司机。 选通电路包括选通线，第一选通驱动器具有第一使能输入，用于启用第一选通驱动器，并且适于用第一选通信号驱动选通线;以及第二选通驱动器，具有第二使能输入， 选通驱动器，并且适于用第二选通信号驱动频闪线。 第一选通控制器耦合到第二使能输入，并且适于使第二选通驱动器在第一选通驱动器被使能的同时预驱动第二选通信号，其中第一和第二选通信号处于相等的逻辑电平。

公开(公告)号：US5581473A

公开(公告)日：1996-12-03

申请号：US605800

申请日：1996-02-23

申请人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

发明人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  Y10S707/99931

摘要： A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository. The timing constraint generator in cooperation with the timing model generator and at least one timing analysis tool generates the timing constraints for the various functional block instances, using the stored information in the repository, the generated timing models of the functional blocks, and a number of timing analysis scripts.

摘要翻译： 提供存储库，加载器，模型生成器，约束生成器和多个时序分析工具，用于管理定时需求规范和测量，以及生成VLSI电路的定时模型和约束。 存储库存储每个针脚实例的时序规格和测量值，每个流程通过圆弧实例。 定时规范和测量由其类别标识，包括至少一个当前规范类别和至少一个测量类别，用于一个时序分析工具。 另外，存储库存储每个引脚实例的多个特性，每个网络的引脚组成以及功能块实例的分层关系。 加载器将各种信息加载到存储库中。 定时模型生成器使用存储库中存储的信息生成各种功能块的时序模型。 与定时模型发生器和至少一个定时分析工具协作的时序约束生成器使用存储库中存储的信息，生成的功能块的定时模型和多个功能块的时间模型来生成各种功能块实例的时序约束 时序分析脚本。

公开(公告)号：US20140184349A1

公开(公告)日：2014-07-03

申请号：US13730629

申请日：2012-12-28

申请人： Harry Muljono ,  Donald L. Faw ,  Charlie Lin ,  Stefan Rusu

发明人： Harry Muljono ,  Donald L. Faw ,  Charlie Lin ,  Stefan Rusu

IPC分类号： H03K7/02

CPC分类号： H03K7/02

摘要： Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

摘要翻译： 用于配置逻辑以实现信号调制的技术和机制。 在一个实施例中，逻辑包括包括电路的有限脉冲响应（FIR）模块。 选择电路可以用于同时从FIR模块的锁存电路接收信号，并且基于该信号来选择选择电路的输入组并输出电压标识符。 在另一个实施例中，配置逻辑可操作以设置操作模式，其确定由FIR模块接收的并发输入信号的总数，FIR模块将使用该模式来选择用于生成表示电压电平的输出的输入组。

公开(公告)号：US20090089607A1

公开(公告)日：2009-04-02

申请号：US11906008

申请日：2007-09-29

申请人： Jorge Rodriguez ,  Alon Naveh ,  Gil Schwarzband ,  Hung-Piao Ma ,  Stefan Rusu ,  James G. Hermerding ,  Ishmael F. Santos ,  Joseph T. Dibene, II ,  Edward Stanford

发明人： Jorge Rodriguez ,  Alon Naveh ,  Gil Schwarzband ,  Hung-Piao Ma ,  Stefan Rusu ,  James G. Hermerding ,  Ishmael F. Santos ,  Joseph T. Dibene, II ,  Edward Stanford

IPC分类号： G06F1/26

CPC分类号： G06F1/26

摘要： Systems and method for providing a regulated voltage supply to an integrated circuit. In an embodiment of the invention, a voltage regulator in a system provides an integrated circuit in the system with information related to the voltage regulator providing a supply voltage to the integrated circuit. In another embodiment of the invention, the integrated circuit makes determinations about the operating characteristic of the system using information from the voltage regulator.

摘要翻译： 向集成电路提供稳压电源的系统和方法。 在本发明的一个实施例中，系统中的电压调节器为系统中的集成电路提供与电压调节器相关的信息，以向集成电路提供电源电压。 在本发明的另一实施例中，集成电路使用来自电压调节器的信息来确定系统的工作特性。

公开(公告)号：US07069455B2

公开(公告)日：2006-06-27

申请号：US10611079

申请日：2003-06-30

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： G06F1/26 ,  H03K3/00

CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292 ,  Y02D30/30

摘要： A driver of a first component and a receiver of a second component of a system are equipped to operate at least one of the driver and the receiver in a low power consumption state, during at least a portion of a quiescent state, when transmitting data from the first to the second component differentially, via a link interface with two lines, coupling the components. The driver and the receiver include respective monitor circuits to detect for the quiescent state, with the driver's monitor circuit monitoring for constancy over a predetermined period, and the receiver's monitor circuit monitoring for zero states on both lines. Further, in one embodiment, the driver's monitor circuit places the driver in the low power consumption state by grounding the two lines.

摘要翻译： 在系统的第二部件的第一部件和接收器的驱动器被配备为在静止状态的至少一部分期间以低功耗状态操作驱动器和接收器中的至少一个，当从 第一个到第二个组件差别化，通过一个具有两条线的链接界面，耦合这些组件。 驱动器和接收器包括用于检测静止状态的各个监视器电路，其中驾驶员的监视器电路在预定时间段内监视恒定状态，并且接收器的监视器电路监视两条线路上的零状态。 此外，在一个实施例中，驾驶员监视器电路通过使两条线路接地来将驾驶员置于低功耗状态。

公开(公告)号：US06762629B2

公开(公告)日：2004-07-13

申请号：US10206610

申请日：2002-07-26

申请人： Simon M. Tam ,  Stefan Rusu

发明人： Simon M. Tam ,  Stefan Rusu

IPC分类号： H03B1900

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3296 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/18 ,  H03L7/22 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and an apparatus for dynamically varying a clock frequency in a processor to adapt to VCC voltage changes. The method of one embodiment includes sampling a supply voltage at a plurality of locations. The values of said supply voltage are communicated to a clock generator. A clock frequency of a clock signal generated from the clock generator is adjusted in response to an evaluation of the sampled values of the supply voltage.

摘要翻译： 一种用于在处理器中动态地改变时钟频率以适应VCC电压变化的方法和装置。 一个实施例的方法包括对多个位置处的电源电压进行采样。 所述电源电压的值被传送到时钟发生器。 响应于对电源电压的采样值的评估，调整从时钟发生器产生的时钟信号的时钟频率。

公开(公告)号：US06707118B2

公开(公告)日：2004-03-16

申请号：US10298756

申请日：2002-11-18

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： H01L2994

CPC分类号： H01L27/08 ,  H01L27/0794 ,  H01L27/0802 ,  H01L29/7841 ,  H01L29/78612

摘要： A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the floating body The floating body provides a distributed capacitance and resistance along its length to form an integrated RC circuit. The extent of the resistance is a function of the cross-sectional area of the floating body along the source and drain regions and its capacitance is a function of the spacing between the doped regions and the body and between the gate and the body. In some embodiments of the present invention, compensation for input voltage variations may be achieved.

摘要翻译： 半导体器件可以形成有位于半导体结构中的绝缘体上方的浮动体。 门可以形成在浮体上方但与之隔开。 半导体结构可以包括围绕浮体的掺杂区域。浮体沿其长度提供分布的电容和电阻以形成集成的RC电路。 电阻的程度是浮体沿着源区和漏极区的横截面面积的函数，其电容是掺杂区与体之间以及栅与体之间的间隔的函数。 在本发明的一些实施例中，可以实现对输入电压变化的补偿。

公开(公告)号：US06524897B1

公开(公告)日：2003-02-25

申请号：US09540117

申请日：2000-03-31

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： H01L2100

CPC分类号： H01L27/08 ,  H01L27/0794 ,  H01L27/0802 ,  H01L29/7841 ,  H01L29/78612

摘要： A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the floating body. The floating body provides a distributed capacitance and resistance along its length to form an integrated RC circuit. The extent of the resistance is a function of the cross-sectional area of the floating body along the source and drain regions and its capacitance is a function of the spacing between the doped regions and the body and between the gate and the body. In some embodiments of the present invention, compensation for input voltage variations may be achieved.

摘要翻译： 半导体器件可以形成有位于半导体结构中的绝缘体上方的浮动体。 门可以形成在浮体上方但与之隔开。 半导体结构可以包括围绕浮体的掺杂区域。 浮体沿其长度提供分布式电容和电阻，形成一个集成的RC电路。 电阻的程度是浮体沿着源区和漏极区的横截面面积的函数，其电容是掺杂区与体之间以及栅与体之间的间隔的函数。 在本发明的一些实施例中，可以实现对输入电压变化的补偿。