公开(公告)号：US08301930B2

公开(公告)日：2012-10-30

申请号：US12356804

申请日：2009-01-21

申请人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC分类号： H04L7/02 ,  H04L7/0025 ,  H04L7/0091

摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

摘要翻译： 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

公开(公告)号：US07996731B2

公开(公告)日：2011-08-09

申请号：US11592074

申请日：2006-11-01

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F11/00

CPC分类号： G06F11/10

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

公开(公告)号：US08429356B2

公开(公告)日：2013-04-23

申请号：US11359809

申请日：2006-02-22

申请人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F13/00

CPC分类号： G06F12/00 ,  G06F13/4234 ,  G06F13/4243 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

摘要翻译： 描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。 实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。 不使用专用的掩码引脚或专用掩码线。 在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。 在一个实施例中，掩模数据作为写入命令的一部分被发送。

公开(公告)号：US07869525B2

公开(公告)日：2011-01-11

申请号：US11357291

申请日：2006-02-17

申请人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： H04B3/00

CPC分类号： H04L25/4915 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.

摘要翻译： 描述了动态总线反演（DBI）方法和系统。 在各种实施例中，发射机通过多比特高速总线向接收机发送数据。 在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。 如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。 在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。 接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。

公开(公告)号：US20070222787A1

公开(公告)日：2007-09-27

申请号：US11746453

申请日：2007-05-09

申请人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

发明人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC分类号： G06T1/00

CPC分类号： G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

摘要： A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

摘要翻译： 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

公开(公告)号：US20060202941A1

公开(公告)日：2006-09-14

申请号：US10906852

申请日：2005-03-09

申请人： Stephen Morein ,  Larry Seiler ,  Michael Doggett ,  Jocelyn Houle

发明人： Stephen Morein ,  Larry Seiler ,  Michael Doggett ,  Jocelyn Houle

IPC分类号： G09G3/36

CPC分类号： G06T15/50 ,  G06T15/005 ,  G06T15/60 ,  G06T15/80 ,  G06T2215/12

摘要： A graphics processing circuit includes a pixel shader operative to provide pixel color information in response to image data representing a scene to be rendered; a texture circuit, coupled to the pixel shader, operative to determine a luminance value to be applied to a pixel of interest based on the luminance values of the pixels that define a plane including the pixel of interest; and a render back end circuit, coupled to the texture circuit, operative to compute the luminance values from a shadow map that specifies the distance from the light source of the nearest object at a plurality of locations. A pixel illumination method includes receiving color information for a pixel to be rendered, defining a plane containing at least one pixel of interest, the plane including a plurality of planar values; comparing the plurality of planar values to a corresponding set of distance values; determining a luminance value for the at least one pixel of interest; and applying the luminance value to the at least one pixel of interest.

摘要翻译： 图形处理电路包括像素着色器，用于响应于表示要渲染的场景的图像数据而提供像素颜色信息; 耦合到像素着色器的纹理电路，用于基于限定包括感兴趣像素的平面的像素的亮度值来确定要施加到感兴趣像素的亮度值; 以及耦合到纹理电路的渲染后端电路，用于从阴影图计算亮度值，所述阴影贴图指定在多个位置处距离最近物体的光源的距离。 像素照明方法包括：接收要渲染的像素的颜色信息，定义包含至少一个感兴趣像素的平面，所述平面包括多个平面值; 将所述多个平面值与相应的一组距离值进行比较; 确定所述感兴趣的所述至少一个像素的亮度值; 以及将所述亮度值应用于所述至少一个感兴趣的像素。

公开(公告)号：US06720964B1

公开(公告)日：2004-04-13

申请号：US09457648

申请日：1999-12-09

申请人： Mark C. Fowler ,  Stephen Morein ,  Andi Skende ,  Kevin M. Olson

发明人： Mark C. Fowler ,  Stephen Morein ,  Andi Skende ,  Kevin M. Olson

IPC分类号： G06T1540

CPC分类号： G06T15/405

摘要： A method and apparatus for processing portions of primitives that are being rendered is presented. Primitives that are received are divided into portions that correspond to pixel blocks of the frame. The frame includes a plurality of pixel blocks where each of the pixel blocks includes a plurality of pixels that are included in the frame. Thus, the pixel blocks divide the frame into a number of smaller blocks. A representative Z value for each portion of the primitive is determined, and the representative Z value for the portion of the primitive is compared with a representative buffered Z, which may be the representative buffer Z value for the pixel block to which the portion corresponds. If the representative Z value for the portion compares favorably with the representative buffered Z value such that the portion is determined to lie completely behind the information currently stored for that pixel block, the portion is discarded. If the representative Z value for the portion compares with the representative buffer Z value in such a way that not all of the portion is ensured of being positioned behind currently buffered data for the pixel block, the portion of the primitive is processed further such that pixel fragments corresponding to the portion are generated and combined with the information currently stored for that pixel block. The representative buffered Z values for each of the pixel blocks may be derived based on a compression scheme applied to the Z values for each of the individual pixel blocks.

摘要翻译： 呈现用于处理正在呈现的图元的部分的方法和装置。 被接收的原语被分成对应于帧的像素块的部分。 该帧包括多个像素块，其中每个像素块包括包括在帧中的多个像素。 因此，像素块将帧划分成多个较小的块。 确定基元的每个部分的代表性的Z值，并将原始部分的代表Z值与代表性的缓冲Z进行比较，代表性的缓冲Z可以是该部分对应的像素块的代表性缓冲器Z值。 如果该部分的代表Z值与代表性缓冲的Z值相比有利地被确定为完全落在当前为该像素块存储的信息之后，则该部分被丢弃。 如果该部分的代表Z值与代表性缓冲器Z值相比较，使得不保证所有部分都被定位在像素块的当前缓冲数据的后面，则进一步处理原语的该部分，使得像素 产生与该部分相对应的片段，并与当前为该像素块存储的信息组合。 可以基于应用于每个像素块的Z值的压缩方案来导出每个像素块的代表性缓冲的Z值。

公开(公告)号：US20110216077A1

公开(公告)日：2011-09-08

申请号：US13109738

申请日：2011-05-17

申请人： Stephen Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Stephen Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06F15/00 ,  G06T1/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US20070222786A1

公开(公告)日：2007-09-27

申请号：US11746446

申请日：2007-05-09

申请人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

发明人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC分类号： G06T1/00

CPC分类号： G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

摘要： A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

摘要翻译： 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。 仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

公开(公告)号：US07239322B2

公开(公告)日：2007-07-03

申请号：US10673761

申请日：2003-09-29

申请人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

发明人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC分类号： G06T1/00 ,  G06F13/18 ,  G06F15/80

CPC分类号： G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

摘要： The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.

摘要翻译： 本发明包括一种多线程图形处理系统及其方法，该系统包括具有存储在其中的多个命令线程的保留站。 该系统和方法还包括可操作地耦合到保留站的仲裁器，使得仲裁器检索存储在其中的多个命令线程的第一命令线程，使得仲裁器接收命令线程，并且随后向命令处理引擎提供命令线程 。 该系统和方法还包括命令处理引擎，其被耦合以从仲裁器接收第一命令线程，使得命令处理器可以从命令线程执行至少一个处理命令。 因此，命令处理引擎将第一命令线程提供给相关联的保留站。