公开(公告)号：US20090285022A1

公开(公告)日：2009-11-19

申请号：US12382176

申请日：2009-03-10

申请人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

发明人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

IPC分类号： G11C16/02 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3418

摘要： A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage.

摘要翻译： 存储器编程方法可以包括基于要在所述多个存储器单元中的至少一个存储器单元中编程的数据的模式来改变要改变的阈值电压的多个存储器单元中的至少一个，将程序条件电压施加到 所述至少一个所识别的存储器单元，直到所述至少一个所识别的存储单元的阈值电压被包括在第一阈值电压间隔内，从而调整所述至少一个识别的存储单元的阈值电压，并且对所述存储单元中的数据进行编程 具有调整的阈值电压的至少一个识别的存储器单元。

公开(公告)号：US20090091990A1

公开(公告)日：2009-04-09

申请号：US12081453

申请日：2008-04-16

申请人： Sung Chung Park ,  Heeseok Eun ,  Seung-Hwan Song ,  Jun Jin Kong ,  Dong Hyuk Chae

发明人： Sung Chung Park ,  Heeseok Eun ,  Seung-Hwan Song ,  Jun Jin Kong ,  Dong Hyuk Chae

IPC分类号： G11C7/00

CPC分类号： G11C11/5628

摘要： Disclosed are a multi-bit programming apparatus and a multi-bit programming method. The multi-bit programming apparatus may include a first control unit that may generates 2N threshold voltage states based on a target bit error rate (BER) of each of the page programming operations, a second control unit that may assign any one of the threshold voltage states to the N-bit data, and a programming unit that may program the assigned threshold voltage state in each of the at least one multi-bit cell to program the N-bit data.

摘要翻译： 公开了一种多位编程装置和多位编程方法。 多位编程设备可以包括第一控制单元，其可以基于每个页面编程操作的目标误码率（BER）产生2N个阈值电压状态;第二控制单元，其可以分配阈值电压 状态到N位数据，以及编程单元，其可以对所述至少一个多位单元中的每一个中的分配的阈值电压状态进行编程以编程N位数据。

公开(公告)号：US20090027971A1

公开(公告)日：2009-01-29

申请号：US12073842

申请日：2008-03-11

申请人： Seung-Hwan Song ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Seung Hoon Lee ,  Dongku Kang

发明人： Seung-Hwan Song ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Seung Hoon Lee ,  Dongku Kang

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C2211/5634

摘要： In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the received voltage value. The at least one first voltage range includes a first upper limit voltage value and a first lower limit voltage value. A data value of the memory cell is set as a first data value when the received voltage value is within the specific voltage range.

摘要翻译： 在从存储单元读取数据时，确定电路通过使用感测与接收电压值对应的输出电流的半导体器件的一次读取操作来确定接收电压值是否在至少一个第一电压范围内。 所述至少一个第一电压范围包括第一上限电压值和第一下限电压值。 当接收电压值在特定电压范围内时，存储单元的数据值被设置为第一数据值。

公开(公告)号：US08667365B2

公开(公告)日：2014-03-04

申请号：US12256784

申请日：2008-10-23

申请人： Nam Phil Jo ,  Dong Hyuk Chae ,  Sung Chung Park ,  Dong Gu Kang

发明人： Nam Phil Jo ,  Dong Hyuk Chae ,  Sung Chung Park ,  Dong Gu Kang

IPC分类号： G06F11/00

CPC分类号： G11C7/1042 ,  G06F11/1068 ,  G06F13/4239

摘要： A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices.

摘要翻译： 存储器系统包括多个存储器件，被配置为控制多个存储器件的控制器以及连接在多个存储器件与控制器之间的至少一个通道。 所述至少一个通道包括与所述多个存储器件连接的输入/输出数据线和控制信号线以及分别连接到所述多个存储器件中的每一个的芯片使能信号线，其中所述芯片使能信号线使得能够 多个存储设备独立。 控制器向多个存储器件之一发送读取命令或程序命令，并且当多个存储器件中的一个存储器件响应于读取命令执行内部读取操作时，控制器从另一个 多个存储器件，或者当多个存储器件中的一个存储器件响应于程序命令执行内部程序操作时，控制器将数据编程到多个存储器件中的另一个。

公开(公告)号：US08239747B2

公开(公告)日：2012-08-07

申请号：US12216744

申请日：2008-07-10

申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

IPC分类号： G06F11/00

CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

公开(公告)号：US08122329B2

公开(公告)日：2012-02-21

申请号：US12929161

申请日：2011-01-05

申请人： Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

发明人： Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G11C29/42 ,  G06F11/1068 ,  G11C11/5628 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

摘要： Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

摘要翻译： 提供各种读取级别控制装置和方法。 在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及 读数据。 该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

公开(公告)号：US08059467B2

公开(公告)日：2011-11-15

申请号：US12382351

申请日：2009-03-13

申请人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

发明人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

摘要： Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

摘要翻译： 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。

公开(公告)号：USD644566S1

公开(公告)日：2011-09-06

申请号：US29372872

申请日：2011-01-25

申请人： Dong Hyuk Chae

设计人： Dong Hyuk Chae

公开(公告)号：US20110145663A1

公开(公告)日：2011-06-16

申请号：US12929161

申请日：2011-01-05

申请人： Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

发明人： Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

IPC分类号： G06F11/00

CPC分类号： G11C29/42 ,  G06F11/1068 ,  G11C11/5628 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

摘要： Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

摘要翻译： 提供各种读取级别控制装置和方法。 在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及 读数据。 该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

公开(公告)号：US07929346B2

公开(公告)日：2011-04-19

申请号：US12216745

申请日：2008-07-10

申请人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

发明人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

IPC分类号： G11C16/06 ,  G11C16/34 ,  G11C16/26

CPC分类号： G11C7/1006 ,  G11C7/14 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C2211/5634

摘要： Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.

摘要翻译： 示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。 示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据 比较结果，用于验证所确定的值是否发生错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据 确定器，以基于所确定的第二参考电压重新确定数据的值。