公开(公告)号：US08051561B2

公开(公告)日：2011-11-08

申请号：US12133414

申请日：2008-06-05

申请人： Eung-yeoul Yoon ,  Kae-dong Back ,  Kyu-ho Shin ,  Jin-seung Choi

发明人： Eung-yeoul Yoon ,  Kae-dong Back ,  Kyu-ho Shin ,  Jin-seung Choi

IPC分类号： H01R43/00 ,  H05K13/00

CPC分类号： G03G15/32 ,  G03G15/751 ,  Y10T29/49002 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174 ,  Y10T29/49227

摘要： A method of manufacturing an image drum includes fixing a control circuit board inside the drum body so that a plurality of terminals of the control circuit board are located in the slot formed longitudinally on the drum body, forming an insulation layer to the entire external surface of the drum body, forming connection parts by removing parts of the insulation layer where the terminals of the control circuit board are formed, forming electrode forming grooves including the insulation layer as a base on the external surface of the drum body comprising the connection parts thereon, and forming a plurality of ring electrodes to be connected to respective terminals among the plurality of the terminals, respectively, through the connection parts.

摘要翻译： 一种制造图象滚筒的方法包括将控制电路板固定在滚筒本体内部，使得控制电路板的多个端子位于纵向形成在滚筒主体上的槽中，在绝缘层的整个外表面上形成绝缘层 通过去除形成控制电路板的端子的绝缘层的部分来形成连接部分，在其上包括连接部分的滚筒主体的外表面上形成包括绝缘层作为基底的电极形成槽， 并且分别通过连接部分形成多个环形电极以分别连接到多个端子中的各个端子。

公开(公告)号：US07579685B2

公开(公告)日：2009-08-25

申请号：US11339500

申请日：2006-01-26

申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

IPC分类号： H01L23/12 ,  H01L23/043

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

摘要翻译： 提供了一种用于晶片级封装的晶片级封装盖及其方法。 覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线 盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和 填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫 并且电连接到多个连接杆。

公开(公告)号：US20080156651A1

公开(公告)日：2008-07-03

申请号：US12000378

申请日：2007-12-12

申请人： Youn-seon Kang ,  Kae-dong Back ,  Woong-chul Shin ,  Seung-jin Oh

发明人： Youn-seon Kang ,  Kae-dong Back ,  Woong-chul Shin ,  Seung-jin Oh

IPC分类号： B05D1/36 ,  C25D5/54

CPC分类号： H01L27/2436 ,  C25D3/56 ,  C25D5/50 ,  C25D7/12 ,  C25D9/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1683

摘要： Provided are a method of forming a phase change layer, a method of manufacturing a storage node using the method of forming a phase change layer, and a method of manufacturing a phase change memory device using the method of manufacturing a storage node. The method of forming a phase change layer may use an electrochemical deposition (ECD) method. The method of forming the phase change layer may include forming an electrolyte by mixing a solvent and precursors, each precursor containing an element of the phase change layer, dipping an anode plate and a cathode plate in the electrolyte to be spaced apart from each other, wherein the cathode plate may be a substrate on which the phase change layer is to be deposited, setting deposition conditions of the phase change layer; and supplying a voltage between the anode plate and the cathode plate.

摘要翻译： 提供了形成相变层的方法，使用形成相变层的方法制造存储节点的方法，以及使用制造存储节点的方法制造相变存储器件的方法。 形成相变层的方法可以使用电化学沉积（ECD）方法。 形成相变层的方法可以包括通过混合溶剂和前体形成电解质，每个前体含有相变层的元素，将阳极板和阴极板浸入电解液中以彼此间隔开， 其中所述阴极板可以是其上将沉积相变层的衬底，设定相变层的沉积条件; 并在阳极板和阴极板之间提供电压。

公开(公告)号：US07786573B2

公开(公告)日：2010-08-31

申请号：US11481012

申请日：2006-07-06

申请人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

发明人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

IPC分类号： H01L23/34 ,  H01R12/16 ,  H05K1/11

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H9/0547

摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

摘要翻译： 形成有多个晶片的封装芯片。 封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。 多个晶片中的至少一个或多个在其上安装预定的电路装置。 此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。 同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。 因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

公开(公告)号：US20060286798A1

公开(公告)日：2006-12-21

申请号：US11412900

申请日：2006-04-28

申请人： Moon-chul Lee ,  Jong-oh Kwon ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

发明人： Moon-chul Lee ,  Jong-oh Kwon ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

IPC分类号： H01L21/44

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L23/04 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

摘要： A cap for a semiconductor device package, including a body formed at a predetermined thickness with a cavity. The cap further includes a first seed layer formed on an inner circumference of a first via hole formed at a predetermined depth from the cavity formation surface of the body, a second seed layer formed on an inner circumference of a second via hole formed at a predetermined depth from the opposite surface to the cavity formation surface of the body, and plating materials filled in the first via hole and the second via hole.

公开(公告)号：US20060175707A1

公开(公告)日：2006-08-10

申请号：US11339500

申请日：2006-01-26

申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

IPC分类号： H01L23/52

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.