公开(公告)号：US11948886B2

公开(公告)日：2024-04-02

申请号：US17244058

申请日：2021-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L23/528 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L29/0696

Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.

公开(公告)号：US11942420B2

公开(公告)日：2024-03-26

申请号：US17835281

申请日：2022-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US11764155B2

公开(公告)日：2023-09-19

申请号：US17728007

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chun Tien ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Shun Li Chen ,  Ting Yu Chen

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/0924

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

公开(公告)号：US11552069B1

公开(公告)日：2023-01-10

申请号：US17463241

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

IPC: H01L27/02 ,  G06F1/3287

Abstract: An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.

公开(公告)号：US11526647B2

公开(公告)日：2022-12-13

申请号：US17115436

申请日：2020-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu Lu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jerry Chang Jui Kao ,  Pin-Dai Sue ,  Jiun-Jia Huang ,  Yu-Ti Su ,  Wei-Hsiang Ma

IPC: G06F30/394 ,  G03F1/70 ,  G03F1/36 ,  G06F30/398

Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.

公开(公告)号：US11508661B2

公开(公告)日：2022-11-22

申请号：US16936249

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu ,  Shih-Ming Chang

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/39 ,  G06F30/392

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

公开(公告)号：US20220352166A1

公开(公告)日：2022-11-03

申请号：US17863175

申请日：2022-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Lun Chien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue

IPC: H01L27/092 ,  H01L23/528 ,  H01L23/522 ,  H01L21/765 ,  H01L21/8238

Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

公开(公告)号：US20210297068A1

公开(公告)日：2021-09-23

申请号：US17339121

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

IPC: H03K3/3562 ,  G01R31/3185 ,  H01L27/092

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

公开(公告)号：US10970440B2

公开(公告)日：2021-04-06

申请号：US16895803

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mao-Wei Chiu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Chi-Yu Lu

IPC: G06F30/30 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L23/528 ,  H01L27/02 ,  G06F115/08

Abstract: A method of manufacturing a semiconductor device (for a layout diagram stored on a non-transitory computer-readable medium) includes generating the layout diagram. The generating the layout diagram includes: placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area; selecting a first pitch for additional cells to be placed in the spare region, wherein use of the first pitch minimizes wasted space in the spare region; selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and placing the selected SNYP spare cells into the spare region of the layout diagram.

公开(公告)号：US20200006217A1

公开(公告)日：2020-01-02

申请号：US16563215

申请日：2019-09-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Sheng-Hsiung Wang

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.