公开(公告)号：US12224241B2

公开(公告)日：2025-02-11

申请号：US17725300

申请日：2022-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Ming Chang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535

Abstract: In a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive pattern and the first ILD layer, a via contact is formed in the second ILD layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer, and a third ILD layer is formed over the second ILD layer.

公开(公告)号：US20210366726A1

公开(公告)日：2021-11-25

申请号：US17397756

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC: H01L21/321 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/522

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US11145519B2

公开(公告)日：2021-10-12

申请号：US16229764

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.

公开(公告)号：US10665467B2

公开(公告)日：2020-05-26

申请号：US15357203

申请日：2016-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun Liu ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Chih-Ming Lai ,  Chia-Ying Lee ,  Jyu-Horng Shieh ,  Ken-Hsien Hsieh ,  Ming-Feng Shieh ,  Shau-Lin Shue ,  Shih-Ming Chang ,  Tien-I Bao ,  Tsai-Sheng Gau

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105

Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.

公开(公告)号：US10528693B2

公开(公告)日：2020-01-07

申请号：US15357716

申请日：2016-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Kuei-Liang Lu

IPC: G06F17/50 ,  H01L23/52 ,  H01L21/027 ,  H01L27/02 ,  H01L23/528 ,  G03F1/00

Abstract: An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.

公开(公告)号：US20190131291A1

公开(公告)日：2019-05-02

申请号：US16220174

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L27/02 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308 ,  H01L21/033 ,  H01L29/06 ,  H01L21/3213

CPC classification number: H01L27/0207 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0657

Abstract: Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.

公开(公告)号：US10001698B2

公开(公告)日：2018-06-19

申请号：US14969182

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36 ,  G06F17/5072

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and a second main feature; determining that the first main feature includes has a curvilinear-based shaped; determining that the second main feature has a polygon-based shape; and mapping a first portion of the IC design layout that includes the first main feature onto a polar coordinate and mapping a second portion of the IC design layout that includes the second main feature on onto a Cartesian coordinate.

公开(公告)号：US20180138042A1

公开(公告)日：2018-05-17

申请号：US15852129

申请日：2017-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen-Chun Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L21/0338 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32139

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

公开(公告)号：US20180047672A1

公开(公告)日：2018-02-15

申请号：US15724899

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chih-Tsung Shih

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/5283 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226

Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.

公开(公告)号：US09852908B2

公开(公告)日：2017-12-26

申请号：US15174131

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen-Chun Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0338 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32139

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.