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    FLIP-FLOP WITH DELINEATED LAYOUT FOR REDUCED FOOTPRINT
    2.
    发明申请
    FLIP-FLOP WITH DELINEATED LAYOUT FOR REDUCED FOOTPRINT 有权

    公开(公告)号：US20210297068A1

    公开(公告)日：2021-09-23

    申请号：US17339121

    申请日：2021-06-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

    IPC分类号： H03K3/3562 ,  G01R31/3185 ,  H01L27/092

    摘要： In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

    Channel doping extension beyond cell boundaries
    3.
    发明授权
    Channel doping extension beyond cell boundaries 有权
    通道掺杂扩展超出单元边界

    公开(公告)号：US09171926B2

    公开(公告)日：2015-10-27

    申请号：US14543991

    申请日：2014-11-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

    IPC分类号： H01L21/8236 ,  H01L29/66 ,  H01L27/02 ,  H01L27/118 ,  H01L27/07 ,  H01L21/8234

    CPC分类号： H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

    摘要： An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

    摘要翻译： 集成电路包括第一和第二标准单元。 第一标准单元包括第一栅极电极和第一栅极电极下面的第一沟道区域。 第一通道区域具有第一通道掺杂浓度。 第二标准单元包括第二栅极电极和第二栅极电极下面的第二沟道区域。 第二沟道区具有第二沟道掺杂浓度。 虚拟栅极分别包括第一和第二标准单元中的前半部分和第二半部分。 第一半和第二半分别在第一标准单元和第二标准单元的边缘处并且彼此抵接。 虚拟通道由虚拟门重叠。 虚拟通道具有基本上等于第一通道掺杂浓度和第二通道掺杂浓度之和的第三通道掺杂浓度。

    Channel doping extension beyond cell boundaries
    4.
    发明授权
    Channel doping extension beyond cell boundaries 有权

    公开(公告)号：US08937358B2

    公开(公告)日：2015-01-20

    申请号：US13874055

    申请日：2013-04-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

    IPC分类号： H01L21/70 ,  H01L27/07

    CPC分类号： H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

    摘要： An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

    Method and system of expanding set of standard cells which comprise a library
    6.
    发明授权
    Method and system of expanding set of standard cells which comprise a library 有权

    公开(公告)号：US10664565B2

    公开(公告)日：2020-05-26

    申请号：US15936712

    申请日：2018-03-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chi-Lin Liu ,  Sheng-Hsiung Chen ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma

    IPC分类号： G06F17/50

    摘要： A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.

    Cell having shifted boundary and boundary-shift scheme
    7.
    发明授权
    Cell having shifted boundary and boundary-shift scheme 有权
    移位边界和边界移位方案

    公开(公告)号：US09262573B2

    公开(公告)日：2016-02-16

    申请号：US13791406

    申请日：2013-03-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5081

    摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

    摘要翻译： 实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。 在一个实施例中，小区移位方案包括移动位置和路由边界以防止布局与示意图（LVS）网表和后仿真网表之间的不匹配。

    Cell and macro placement on fin grid
    8.
    发明授权
    Cell and macro placement on fin grid 有权
    细胞和宏放置在鳍状网格上

    公开(公告)号：US09047433B2

    公开(公告)日：2015-06-02

    申请号：US13874027

    申请日：2013-04-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

    摘要翻译： 芯片包括至少一个标准单元，其包括与第一边界相对的第一边界和第二边界。 第一边界和第二边界平行于第一方向。 所述至少一个标准单元还包括第一多个FinFET，其包括平行于所述第一方向的第一半导体鳍片。 芯片还包括至少一个存储器宏，其具有与第三边界相反的第三边界和第四边界。 第三边界和第四边界与第一方向平行。 至少一个存储器宏包括第二多个FinFET，其包括平行于第一方向的第二半导体鳍片。 所述至少一个标准单元和所述至少一个存储器宏中的所有半导体鳍具有等于所述第一和第二半导体鳍的最小间距的整数倍的间距。

    Cell Having Shifted Boundary and Boundary-Shift Scheme
    9.
    发明申请
    Cell Having Shifted Boundary and Boundary-Shift Scheme 有权
    移位边界和边界移位方案

    公开(公告)号：US20140258952A1

    公开(公告)日：2014-09-11

    申请号：US13791406

    申请日：2013-03-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5081

    摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

    摘要翻译： 实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。 在一个实施例中，小区移位方案包括移动位置和路由边界以防止布局与示意图（LVS）网表和后仿真网表之间的不匹配。

    Cell and Macro Placement on Fin Grid
    10.
    发明申请
    Cell and Macro Placement on Fin Grid 有权
    电网和宏放置在电网上

    公开(公告)号：US20140245248A1

    公开(公告)日：2014-08-28

    申请号：US13874027

    申请日：2013-04-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

    摘要翻译： 芯片包括至少一个标准单元，其包括与第一边界相对的第一边界和第二边界。 第一边界和第二边界平行于第一方向。 所述至少一个标准单元还包括第一多个FinFET，其包括平行于所述第一方向的第一半导体鳍片。 芯片还包括至少一个存储器宏，其具有与第三边界相反的第三边界和第四边界。 第三边界和第四边界与第一方向平行。 至少一个存储器宏包括第二多个FinFET，其包括平行于第一方向的第二半导体鳍片。 所述至少一个标准单元和所述至少一个存储器宏中的所有半导体鳍片具有等于所述第一和第二半导体鳍片的最小间距的整数倍的间距。