公开(公告)号：US11743080B2

公开(公告)日：2023-08-29

申请号：US17083008

申请日：2020-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Amit Rane ,  Ashwin Kottilvalappil Vijayan

IPC: H04L27/01 ,  H04L25/03

CPC classification number: H04L27/01 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885 ,  H04L2025/0349

Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.

公开(公告)号：US20230246884A1

公开(公告)日：2023-08-03

申请号：US17588706

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Amit Rane

IPC: H04L25/03 ,  H04B1/16 ,  H03F3/04 ,  H03K17/687

CPC classification number: H04L25/03057 ,  H04B1/16 ,  H03F3/04 ,  H03K17/6872 ,  H03F2200/165

Abstract: Systems, circuitry and methods correct baseline wander while reducing amplitude difference between the input signal to a data sampler and the output signal of an output-swing-controlled buffer. Example baseline wander correction circuitry comprises a baseline wander correction loop that receives an equalized data signal, a feedback signal and a buffer control signal, and corrects baseline wander in the data sampler input signal. Baseline wander correction loop generates the buffer output signal based on the data sampler output signal and the buffer control signal. Baseline wander correction circuitry also comprises a feedback circuit that receives the data sampler output signal and generates the feedback signal, and an amplitude estimation loop that receives the data sampler input and output signals and outputs the buffer control signal to control the peak-to-peak swing of the buffer output signal.

公开(公告)号：US20230135422A1

公开(公告)日：2023-05-04

申请号：US17515034

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Nithin Sathisan Poduval ,  Abishek Manian ,  Roland Nii Ofei Ribeiro

IPC: H03K19/0185 ,  H03K3/037

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

公开(公告)号：US11621715B1

公开(公告)日：2023-04-04

申请号：US17573144

申请日：2022-01-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robin Gupta ,  Abishek Manian

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H03L7/08 ,  H03L7/087 ,  H04L7/033

Abstract: Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.

公开(公告)号：US11239834B2

公开(公告)日：2022-02-01

申请号：US17119050

申请日：2020-12-11

Applicant: Texas Instruments Incorporated

Inventor： Abishek Manian

IPC: H03L7/06 ,  H03K5/14 ,  H03K5/15 ,  H03K19/21 ,  H03K5/06 ,  H03K5/00

Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

公开(公告)号：US10897245B1

公开(公告)日：2021-01-19

申请号：US16687147

申请日：2019-11-18

Applicant: Texas Instruments Incorporated

Inventor： Abishek Manian

IPC: H03L7/06 ,  H03K5/14 ,  H03K5/15 ,  H03K19/21 ,  H03K5/06 ,  H03K5/00

Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

公开(公告)号：US20200084015A1

公开(公告)日：2020-03-12

申请号：US16128818

申请日：2018-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Michael Gerald Vrazel

IPC: H04L7/033 ,  H03L7/087 ,  H03L7/095 ,  H03L7/091 ,  H03L7/093

Abstract: A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.

公开(公告)号：US10236897B1

公开(公告)日：2019-03-19

申请号：US16045930

申请日：2018-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Robin Gupta

IPC: H03L7/06 ,  H03L7/095 ,  H04L7/033 ,  H03L7/08

Abstract: A loss of lock detection circuit includes detection circuitry and pulse accumulation circuitry. The detection circuitry includes a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is configured to synchronize a data stream to a first edge of a clock signal. The second flip-flop is configured to synchronize the data stream to a second edge of the clock signal. The third flip-flop is clocked by the data stream, and is configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream. The pulse accumulation circuitry is coupled to the detection circuitry. The pulse accumulation circuitry is configured to collect pulses generated by the third flip-flop.