公开(公告)号：US20190019776A1

公开(公告)日：2019-01-17

申请号：US15646976

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Minhong Mi ,  Swaminathan Sankaran ,  Rajen M. Murugan ,  Vikas Gupta

IPC: H01L25/065 ,  H01L23/31 ,  H01L49/02 ,  H01L23/495 ,  H01L23/00

Abstract: Described examples include a packaged device including a first object and a second object spaced from each other by a gap, each object having a first surface and an opposite second surface, the first surfaces of the first object and the second object including first terminals. A structure includes at least two conductors embedded in a dielectric casing consolidating a configuration and organization of the at least two conductors, the at least two conductors having end portions un-embedded by the dielectric casing. An end portion of at least one of the at least two conductors is electrically connected to a first terminal of the first object, and an opposite end portion of the at least one of the at least two conductors is electrically connected to a respective first terminal of the second object, the at least two conductors electrically connecting the first object and the second object.

公开(公告)号：US20160322557A1

公开(公告)日：2016-11-03

申请号：US14698616

申请日：2015-04-28

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Abram Castro

IPC: H01L41/08 ,  H03H3/007

CPC classification number: H03H9/1042 ,  H03H9/1007

Abstract: An assembly including an electrical connection substrate formed of material having a Young's modulus of less than about 10 MPa, an acoustic device die having opposite end portions mounted on and electrically connected to the electrical connection substrate and a mold compound layer encapsulating the acoustic device die and interfacing with the substrate.

Abstract translation: 一种组件，包括由杨氏模量小于约10MPa的材料形成的电连接衬底，具有安装在电连接衬底上并与其电连接的相对端部的声学器件模具和封装声学器件裸片的模制化合物层 与基底接触。

公开(公告)号：US20230387043A1

公开(公告)日：2023-11-30

申请号：US18450291

申请日：2023-08-15

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/645 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L21/565 ,  H01L23/49589 ,  H01L28/10 ,  H01L21/4825 ,  H01L23/49575

Abstract: An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

公开(公告)号：US20230187121A1

公开(公告)日：2023-06-15

申请号：US17546287

申请日：2021-12-09

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01F27/32 ,  H01L23/495 ,  H01L23/58 ,  H01F27/02 ,  H01F27/28 ,  H01L23/522 ,  H01L25/00 ,  H01F41/04

CPC classification number: H01F27/323 ,  H01L23/49575 ,  H01L23/58 ,  H01F27/022 ,  H01F27/2804 ,  H01L23/5227 ,  H01L25/50 ,  H01F41/043 ,  H01L23/49555 ,  H01F2027/2809 ,  H01L25/18

Abstract: A magnetic assembly includes a multilevel lamination or metallization structure with a core dielectric layer, dielectric stack layers, a high permittivity dielectric layer, and first and second patterned conductive features, the dielectric stack layers having a first relative permittivity, the high permittivity dielectric layer extends between and contacting the first patterned conductive feature and one of the dielectric stack layers or the core dielectric layer, the high permittivity dielectric layer has a second relative permittivity, and the second relative permittivity is at least 1.5 times the first relative permittivity to mitigate dielectric breakdown in isolation products.

公开(公告)号：US11658101B2

公开(公告)日：2023-05-23

申请号：US17219830

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/49513 ,  H01L23/49558 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/48175

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

公开(公告)号：US20230097816A1

公开(公告)日：2023-03-30

申请号：US17491522

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/60 ,  H01L23/00

Abstract: In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.

公开(公告)号：US11569396B2

公开(公告)日：2023-01-31

申请号：US17088963

申请日：2020-11-04

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L31/0203 ,  H01L31/02 ,  G01J1/02 ,  H01L31/173

Abstract: An optical sensor package includes an IC die including a light sensor element, an output node, and bond pads including a bond pad coupled to the output node. A leadframe includes a plurality of leads or lead terminals, wherein at least some of the plurality of leads or lead terminals are coupled to the bond pads including to the bond pad coupled to the output node. A mold compound provides encapsulation for the optical sensor package including for the light sensor element. The mold compound includes a polymer-base material having filler particles including at least one of infrared or terahertz transparent particle composition provided in a sufficient concentration so that the mold compound is optically transparent for providing an optical transparency of at least 50% for a minimum mold thickness of 500 μm in a portion of at least one of an infrared frequency range and a terahertz frequency range.

公开(公告)号：US11557722B2

公开(公告)日：2023-01-17

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  G01R33/07 ,  G01R15/20 ,  H01L43/06 ,  H01L23/495 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US11552013B2

公开(公告)日：2023-01-10

申请号：US17218941

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/525 ,  H01L23/498 ,  H01L23/00

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, and leads spaced from the die pad; a semiconductor die mounted on the die pad; a fuse mounted to a lead, the fuse having a fuse element coupled between a fuse cap and the lead, the fuse having a fuse body with an opening surrounding the fuse element, the fuse cap attached to the fuse body; electrical connections coupling the semiconductor die to the fuse; and mold compound covering the semiconductor die, the fuse, the electrical connections, and a portion of the package substrate, with portions of the leads exposed from the mold compound to form terminals.

公开(公告)号：US11342251B2

公开(公告)日：2022-05-24

申请号：US17015059

申请日：2020-09-08

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/495

Abstract: A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.