公开(公告)号：US20200209931A1

公开(公告)日：2020-07-02

申请号：US16814625

申请日：2020-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Chunhua Hu ,  Erkan Bilhan ,  Sumant Dinkar Kale

IPC: G06F1/24 ,  G06F1/28

Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.

公开(公告)号：US20190190521A1

公开(公告)日：2019-06-20

申请号：US16284212

申请日：2019-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US10256821B2

公开(公告)日：2019-04-09

申请号：US15437593

申请日：2017-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/017 ,  H03K19/0175 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US20180183434A1

公开(公告)日：2018-06-28

申请号：US15387683

申请日：2016-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Sumant Dinkar Kale ,  Chunhua Hu

IPC: H03K17/22 ,  H03B5/32

CPC classification number: H03K17/22 ,  G06F11/1441 ,  H03B5/32

Abstract: A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.

公开(公告)号：US20170017943A1

公开(公告)日：2017-01-19

申请号：US14799341

申请日：2015-07-14

Applicant: Texas Instruments Incorporated

Inventor： Erkan Bilhan ,  Rajitha Padakanti ,  Amritpal Singh Mundra

IPC: G06Q20/20 ,  G08B13/06

CPC classification number: G06Q20/206 ,  G07F19/2055

Abstract: A financial transaction system includes sensors, a tamper detection module, and circuitry configurable to control which sensors are used, and the circuitry is configurable after the tamper detection module has been manufactured.

Abstract translation: 金融交易系统包括传感器，篡改检测模块和可配置为控制使用哪些传感器的电路，并且在制造篡改检测模块之后可配置电路。

公开(公告)号：US20130187456A1

公开(公告)日：2013-07-25

申请号：US13744664

申请日：2013-01-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan

IPC: H02J4/00

CPC classification number: H02J4/00 ,  G06F1/26 ,  G06F21/86 ,  Y10T307/383

Abstract: This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and analog circuits. A second, lower power supply powers digital circuits and memory. A first voltage monitor circuit powered by said first power supply generates a first output signal when the first power supply is below an operational limit high level. A second voltage monitor circuit powered by said first power supply indicates when the second power supply is above an operational high limit level. A power switch is controlled by the first voltage monitor circuit. This power switch connects the second power supply and second load when closed and isolates them when open. Thus the memory cannot be accessed when the I/O and analog power supply is out of specification.

Abstract translation: 本发明是一种片上系统（SOC），需要两个防篡改外部产生的电源。 第一个更高的电源为I / O和模拟电路供电。 第二个较低的电源为数字电路和存储器供电。 当第一电源低于操作极限高电平时，由所述第一电源供电的第一电压监视器电路产生第一输出信号。 由所述第一电源供电的第二电压监视器电路指示第二电源何时高于操作上限电平。 电源开关由第一电压监视电路控制。 此电源开关在关闭时连接第二个电源和第二个负载，并在打开时将其隔离。 因此，当I / O和模拟电源超出规格时，无法访问存储器。

公开(公告)号：US20240088896A1

公开(公告)日：2024-03-14

申请号：US18516256

申请日：2023-11-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K3/356 ,  H03K19/20

CPC classification number: H03K19/00315 ,  H03K3/356113 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US11626875B2

公开(公告)日：2023-04-11

申请号：US16262327

申请日：2019-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US20200328738A1

公开(公告)日：2020-10-15

申请号：US16912057

申请日：2020-06-25

Applicant: Texas Instruments Incorporated

Inventor： Venkateswar Reddy Kowkutla ,  Chunhua Hu ,  Erkan Bilhan ,  Sumant Dinkar Kale

IPC: H03K17/22 ,  G05B19/042 ,  G06F1/24 ,  G06F1/3296

Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.

公开(公告)号：US10734993B2

公开(公告)日：2020-08-04

申请号：US15393513

申请日：2016-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Chunhua Hu ,  Erkan Bilhan ,  Sumant Dinkar Kale

IPC: G05B19/042 ,  G06F1/24 ,  G06F1/3296 ,  H03K17/22 ,  H03K17/30

Abstract: The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.